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Proceedings Paper

20nm VIA BEOL patterning challenges
Author(s): Chien-Hsien S. Lee; Sohan Singh Mehta; Wontae Hwang; Hui Husan Tsai; Michael Anderson; Yayi Wei; Matthew Herrick; Xiang Hu; Bumhwan Jeon; Shyam Pal
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Paper Abstract

Higher density on 20nm logic chips require tighter pitches to be implemented not only at critical metal layers, but at BEOL critical VIA layers as well. Smaller pitches on critical via are no longer achievable through the conventional positive tone development (PTD) process. Instead, negative tone development (NTD) is considered, evaluated, and integrated as an alternative, along with the double patterning (DP) method. Additionally, preliminary results on NTD+DP patterning challenges, including patterning verification, are presented in this paper.

Paper Details

Date Published: 29 March 2013
PDF: 8 pages
Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 86820D (29 March 2013); doi: 10.1117/12.2011843
Show Author Affiliations
Chien-Hsien S. Lee, GLOBALFOUNDRIES Inc. (United States)
Sohan Singh Mehta, GLOBALFOUNDRIES Inc. (United States)
Wontae Hwang, GLOBALFOUNDRIES Inc. (United States)
Hui Husan Tsai, GLOBALFOUNDRIES Inc. (United States)
Michael Anderson, GLOBALFOUNDRIES Inc. (United States)
Yayi Wei, GLOBALFOUNDRIES Inc. (United States)
Matthew Herrick, GLOBALFOUNDRIES Inc. (United States)
Xiang Hu, GLOBALFOUNDRIES Inc. (United States)
Bumhwan Jeon, GLOBALFOUNDRIES Inc. (United States)
Shyam Pal, GLOBALFOUNDRIES Inc. (United States)

Published in SPIE Proceedings Vol. 8682:
Advances in Resist Materials and Processing Technology XXX
Mark H. Somervell, Editor(s)

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