Time-dependent dielectric breakdown (TDDB) is becoming a critical reliability issue, since the electric field across dielectric increases as technology scales. Moreover, dielectric reliability is aggravated when interconnect spacings vary due to (vias and wires) mask misalignment. Although dielectric reliability can be mitigated by a larger interconnect pitch, such a guardband leads to significant area overhead. In this paper, we propose to improve dielectric reliability through a post-layout optimization. In the layout optimization, we locally shave and/or shift a fraction of wire width to increase the spacing between wires, and/or between adjacent-layer vias and wires. Our experimental results show that the layout optimization can improve interconnect lifetime by 9% to 10%. Separately, we also propose a signal-aware chip-level TDDB reliability estimation method which estimates TDDB stress time of interconnects using net signals obtained from a vectorless analysis. By using the signal-aware analysis method, we show that chip-level TDDB lifetime is approximately twice that obtained using the conventional analysis approach which assumes interconnects are always under electrical stress.

Date Published: 29 March 2013
PDF: 11 pages
Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840L (29 March 2013); doi: 10.1117/12.2011645

Published in SPIE Proceedings Vol. 8684:
Design for Manufacturability through Design-Process Integration VII
Mark E. Mason; John L. Sturtevant, Editor(s)