The migration to a 3D implementation for NAND flash devices is seen as the leading contender to replace traditional planar NAND architectures. However the strategy of replacing shrinking design rules with greater aspect ratios is not without its own set of challenges. The yield-limiting defect challenges for the planar NAND front end were primarily bridges, protrusions and residues at the bottom of the gates, while the primary challenges for front end 3D NAND is buried particles, voids and bridges in the top, middle and bottom of high aspect ratio structures. Of particular interest are the yield challenges in the channel hole process module and developing an understanding of the contribution of litho and etch defectivity for this challenging new integration scheme. The key defectivity and process challenges in this module are missing, misshapen channel holes or under-etched channel holes as well as reducing noise sources related to other none yield limiting defect types and noise related to the process integration scheme. These challenges are expected to amplify as the memory density increases. In this study we show that a broadband brightfield approach to defect monitoring can be uniquely effective for the channel hole module. This approach is correlated to end-of-line (EOL) Wafer Bin Map for verification of capability.

Date Published: 29 March 2013
PDF: 7 pages
Proc. SPIE 8685, Advanced Etch Technology for Nanopatterning II, 86850U (29 March 2013); doi: 10.1117/12.2011435

Published in SPIE Proceedings Vol. 8685:
Advanced Etch Technology for Nanopatterning II
Ying Zhang; Gottlieb S. Oehrlein; Qinghuang Lin, Editor(s)