Proceedings Paper
DSP code optimization based on cache| Format | Member Price | Non-Member Price |
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Paper Abstract
DSP program‟s running efficiency on board is often lower than which via the software simulation during the program development, which is mainly resulted from the user‟s improper use and incomplete understanding of the cache-based memory. This paper took the TI TMS320C6455 DSP as an example, analyzed its two-level internal cache, and summarized the methods of code optimization. Processor can achieve its best performance when using these code optimization methods. At last, a specific algorithm application in radar signal processing is proposed. Experiment result shows that these optimization are efficient.
Paper Details
Date Published: 20 March 2013
PDF: 6 pages
Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87682Q (20 March 2013); doi: 10.1117/12.2010893
Published in SPIE Proceedings Vol. 8768:
International Conference on Graphic and Image Processing (ICGIP 2012)
Zeng Zhu, Editor(s)
PDF: 6 pages
Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87682Q (20 March 2013); doi: 10.1117/12.2010893
Show Author Affiliations
Chengfa Xu, Beijing Institute of Technology (China)
Chengcheng Li, Beijing Institute of Technology (China)
Chengcheng Li, Beijing Institute of Technology (China)
Bin Tang, Beijing Institute of Remote Sensing Equipment (China)
Published in SPIE Proceedings Vol. 8768:
International Conference on Graphic and Image Processing (ICGIP 2012)
Zeng Zhu, Editor(s)
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