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Proceedings Paper

High order wafer alignment for 20nm node logic process
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Paper Abstract

Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).

Paper Details

Date Published: 18 April 2013
PDF: 5 pages
Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 868110 (18 April 2013); doi: 10.1117/12.2010709
Show Author Affiliations
Bumhwan Jeon, GLOBALFOUNDRIES (United States)
Shyam Pal, GLOBALFOUNDRIES (United States)
Sohan Mehta, GLOBALFOUNDRIES (United States)
Subramany Lokesh, GLOBALFOUNDRIES (United States)
Yun Tao Jiang, GLOBALFOUNDRIES (United States)
Chen Li, GLOBALFOUNDRIES (United States)
Mark Yelverton, GLOBALFOUNDRIES (United States)
Yayi Wei, GLOBALFOUNDRIES (United States)

Published in SPIE Proceedings Vol. 8681:
Metrology, Inspection, and Process Control for Microlithography XXVII
Alexander Starikov; Jason P. Cain, Editor(s)

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