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Proceedings Paper

MaxVideo 200: a pipeline image processing architecture for performance-demanding applications
Author(s): Glen L. Ahearn
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Paper Abstract

A variety of hardware architectures have been used to address image processing needs including general purpose processors (CPUs, array processors, and DSPs), parallel processors, and pipeline processors. In performance-demanding imaging applications a pipeline processing architecture, such as MaxVideo 200, has some distinct advantages. MaxVideo 200 is a pipeline processing architecture designed by Datacube for a variety of image processing applications. It consists of many different `algorithmically specific' processing sections that may be used to process the image in stages. These processing sections all operate at a 20 MHz, synchronous rate. Each processing section performs its operation (convolution, arithmetic operation, look-up table, etc...) in a fixed, integer number of clock cycles. The time it takes for each processing section to perform its function is known as pipeline delay. Since the pipeline delay of each section is fixed, the cumulative delay of passing the image data through multiple processing sections can be calculated. This cumulative delay can then be compensated for within the memory architecture of the MaxVideo 200. The memory architecture of the MaxVideo 200 also operates on the same synchronous 20 MHz clock as the processing section. By controlling when the memory acquires the image data after it has been processed, the image may be `realigned' in memory for display or further processing.

Paper Details

Date Published: 31 January 1995
PDF: 4 pages
Proc. SPIE 2368, 23rd AIPR Workshop: Image and Information Systems: Applications and Opportunities, (31 January 1995); doi: 10.1117/12.200800
Show Author Affiliations
Glen L. Ahearn, Datacube, Inc. (United States)

Published in SPIE Proceedings Vol. 2368:
23rd AIPR Workshop: Image and Information Systems: Applications and Opportunities
Peter J. Costianes, Editor(s)

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