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Proceedings Paper

Data point selection for site qualification of wafers for ULSI lithography
Author(s): Randal K. Goodall; Noel S. Poduje
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Paper Abstract

Advanced, automated wafer flatness characterization systems allow flexibility in emulating lithographic systems. Other considerations related to the interaction of an individual characterization system with a lithographic application are becoming more critical with shrinking device geometries. Specifically, all automatic flatness characterization systems use an array of discrete, sampled data points across the surface of the wafer. This paper will show that the definition and location of these points influences the measured site flatness. Situations leading to error are modeled. A distinction is made between the sample array (the points at which data is acquired) and a second analysis array (derived from the first) used for calculation of the site flatness. It is shown that, assuming the sample array meets the Nyquist criteria for the wafer topography of interest, the analysis array may be optimized for that application. Results from measurements made on typical polished wafers are related to the models. A strategy is presented for optimization of the analysis array.

Paper Details

Date Published: 1 June 1990
PDF: 13 pages
Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); doi: 10.1117/12.20051
Show Author Affiliations
Randal K. Goodall, ADE Corp. (United States)
Noel S. Poduje, ADE Corp. (United States)

Published in SPIE Proceedings Vol. 1261:
Integrated Circuit Metrology, Inspection, and Process Control IV
William H. Arnold, Editor(s)

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