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Proceedings Paper

Algorithm-based fault-tolerant array architecture for Fermat number transform
Author(s): Jamel M. Tahir; Satnam Singh Dlay; Raouf N. Gorgui-Naguib; Oliver R. Hinton
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Paper Abstract

For many real-time and scientific applications, it is desirable to perform signal and image processing algorithms by means of special hardware with very high speeds. With the advent of VLSI technology, large collections of processing elements, which cooperate with each other to achieve high-speed computation, have become economically feasible. In such systems, some level of fault tolerance must be obtained to ensure the validity of the results. Fermat number transforms (FNT's) are attractive for the implementation of digital convolution because the computations are carried out in modular arithmetic which involves no round-off error. In this paper we present a fault tolerant linear array design for FNT by adopting the weighted checksum approach. The results show that the approach is ideally suited to the FNT since it offers fault tolerance, with very low cost, free from round-off error and overflow problems.

Paper Details

Date Published: 28 October 1994
PDF: 12 pages
Proc. SPIE 2296, Advanced Signal Processing: Algorithms, Architectures, and Implementations V, (28 October 1994); doi: 10.1117/12.190889
Show Author Affiliations
Jamel M. Tahir, Univ. of Newcastle Upon Tyne (United Kingdom)
Satnam Singh Dlay, Univ. of Newcastle Upon Tyne (United Kingdom)
Raouf N. Gorgui-Naguib, Univ. of Newcastle Upon Tyne (United Kingdom)
Oliver R. Hinton, Univ. of Newcastle Upon Tyne (United Kingdom)


Published in SPIE Proceedings Vol. 2296:
Advanced Signal Processing: Algorithms, Architectures, and Implementations V
Franklin T. Luk, Editor(s)

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