Share Email Print

Proceedings Paper

Memory failure analysis using EB voltage contrast image
Author(s): Hiroyuki Hamada; Tohru Tsujide; Kazuo Nakaizumi
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper presents some novel fault localization techniques for a memory LSI by using an EB tester. Effective techniques for applying pulse combinations of input signals and acquiring images are put forward. Excellent voltage contrast images are acquired on the passivated devices without degradation of voltage contrast from charge up. Signal lines are back-traced by comparing good and bad images to identify the failure point. Application to the failure analysis of DRAMs is successfully performed with minimal time requirements.

Paper Details

Date Published: 14 September 1994
PDF: 8 pages
Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186751
Show Author Affiliations
Hiroyuki Hamada, NEC Corp. (Japan)
Tohru Tsujide, NEC Corp. (Japan)
Kazuo Nakaizumi, NEC Corp. (Japan)

Published in SPIE Proceedings Vol. 2334:
Microelectronics Manufacturability, Yield, and Reliability
Barbara Vasquez; Hisao Kawasaki, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?