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Proceedings Paper

Monitoring of highly selective plasma etch processes
Author(s): Jer-Shen Maa; Lynn R. Allen; Dave Evans; Tzu Yen Hsieh; Bruce D. Ulrich; Sheng Teng Hsu; John M. Grant; Greg Stecker
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Paper Abstract

A very high selectivity is required in most of the plasma etching processes for the fabrication of subhalf micron devices. One of the most critical steps is the polysilicon etch, in which the etch stop layer is a thin oxide of 50 angstrom to 100 angstrom. An extended overetch is generally required to remove polysilicon stringers at the bottom corner of the topological steps. During this overetching step microtrenching can become a problem when the thin oxide film at the bottom corner of the polysilicon structure is removed. In the contact etch a very high selectivity is also required due to the increased aspect ratio and depth variation of the contact holes. High selectivity to the silicon substrate or to the thin silicide layer insures minimal loss of substrate silicon or silicide in the shallow contact region. In spacer etch, especially when dealing with SOI devices using an ultrathin silicon layer, a substantial amount of silicon can be lost if selectivity is not high enough, causing uncertainty in the composition and thickness of the silicide layer formed in the subsequent silicidation step. Oftentimes the problems in these plasma etch processes can not be detected until the device is tested after the completion of the metallization step. Due to the time lag, it is difficult to trace the real causes of the problems. This can represent a significant monetary loss especially when dealing with larger diameter wafers. An inline monitoring method is very essential especially in a high volume production environment. Analytical techniques such as TEM cross sectional work or even high resolution SEM work is difficult to implement as an in-line monitoring method. Controlling the etch processes by measuring the etch selectivity may be very troublesome. Determining a slight change of thickness of the etch stop layer in a highly selective process is quite difficult. Also, in most cases the structure on the test wafers is very different from the actual devices. Important parameters such as percentage of resist coverage or effect of line width and spacing, etc., are mostly ignored.

Paper Details

Date Published: 14 September 1994
PDF: 12 pages
Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186737
Show Author Affiliations
Jer-Shen Maa, Sharp Microelectronics Technology, Inc. (United States)
Lynn R. Allen, Sharp Microelectronics Technology, Inc. (United States)
Dave Evans, Sharp Microelectronics Technology, Inc. (United States)
Tzu Yen Hsieh, Sharp Microelectronics Technology, Inc. (United States)
Bruce D. Ulrich, Sharp Microelectronics Technology, Inc. (United States)
Sheng Teng Hsu, Sharp Microelectronics Technology, Inc. (United States)
John M. Grant, Sharp Microelectronics Technology, Inc. (United States)
Greg Stecker, Sharp Microelectronics Technology, Inc. (United States)

Published in SPIE Proceedings Vol. 2334:
Microelectronics Manufacturability, Yield, and Reliability
Barbara Vasquez; Hisao Kawasaki, Editor(s)

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