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Proceedings Paper

Analysis and design considerations for manufacturable and reliable 0.18-micron N-MOSFETs
Author(s): Shyam Krishnamurthy; S. Jallepalli; ChohFei Yeap; Khaled Hasnat; Christine M. Maziar; Al F. Tasch Jr.
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Paper Abstract

As MOSFET dimensions are scaled, innovative techniques are required to overcome many problems specific to short-channel devices, while retaining the performance enhancement that justifies scaling to smaller dimensions. We present a design methodology and an analysis investigating the design approaches and the trade-offs for simultaneously obtaining high performance, reliable, and manufacturable 0.18 micron n-channel MOSFETs. The results of two-dimensional numerical device simulations of three candidate structural approaches that have been selected based on scalability, reliability, manufacturability, and performance considerations are discussed. The influence of effects such as velocity overshoot and inversion layer quantization on the device behavior and the trends and trade-offs are described.

Paper Details

Date Published: 9 September 1994
PDF: 12 pages
Proc. SPIE 2335, Microelectronics Technology and Process Integration, (9 September 1994); doi: 10.1117/12.186059
Show Author Affiliations
Shyam Krishnamurthy, Univ. of Texas/Austin (United States)
S. Jallepalli, Univ. of Texas/Austin (United States)
ChohFei Yeap, Univ. of Texas/Austin (United States)
Khaled Hasnat, Univ. of Texas/Austin (United States)
Christine M. Maziar, Univ. of Texas/Austin (United States)
Al F. Tasch Jr., Univ. of Texas/Austin (United States)

Published in SPIE Proceedings Vol. 2335:
Microelectronics Technology and Process Integration
Fusen E. Chen; Shyam P. Murarka, Editor(s)

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