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Proceedings Paper

Chemical mechanical planarization of multilayer dielectric stacks
Author(s): Manoj K. Jain; Girish A. Dixit; Michael F. Chisholm; Thomas R. Seha; Kelly J. Taylor; Gregory B. Shinn; Robert H. Havemann
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Paper Abstract

Sub-0.5 micrometers multilevel metal schemes impose stringent requirements on both gap-fill and planarity of interlevel dielectrics. A variety of novel materials and processes are being investigated to meet these process requirements. In this paper, four dielectrics with good gap- filling capabilities are evaluated for planarity characteristics: SiO2 deposited using a high density plasma (HDP) with simultaneous deposition and sputtering, an organic spin-on-glass material SOG-A, an inorganic spin-on-glass material SOG-B, and SiO2 deposited using ozone and TEOS at sub-atmospheric pressure (SACVD). These materials are used for gap-fill followed by a capping layer of PETEOS. For global planarization, only the top layer of PETEOS is planarized using chemical mechanical polishing (CMP) without exposing the underlying gap-fill material. Planarization characteristics of the dielectric stacks are found to be significantly different, both before and after CMP. The CMP throughput is found to be very sensitive to the choice of the dielectric stack. For a given planarity goal, the CMP throughputs of three of the dielectric stacks are found to be significantly higher than that of a conventional single layer interlevel dielectric (ILD) consisting of only PETEOS.

Paper Details

Date Published: 9 September 1994
PDF: 10 pages
Proc. SPIE 2335, Microelectronics Technology and Process Integration, (9 September 1994); doi: 10.1117/12.186045
Show Author Affiliations
Manoj K. Jain, Texas Instruments Inc. (United States)
Girish A. Dixit, Texas Instruments Inc. (United States)
Michael F. Chisholm, Texas Instruments Inc. (United States)
Thomas R. Seha, Texas Instruments Inc. (United States)
Kelly J. Taylor, Texas Instruments Inc. (United States)
Gregory B. Shinn, Texas Instruments Inc. (United States)
Robert H. Havemann, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 2335:
Microelectronics Technology and Process Integration
Fusen E. Chen; Shyam P. Murarka, Editor(s)

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