This paper describes the realization of a TV interlaced to HDTV interlaced real time format converter for studio applications. The conversion is performed by motion compensated 3D- interpolation. The estimation of motion is based on hierarchical blockmatching. Reliability checking of motion vectors is applied to achieve high picture quality. Furthermore various picture classification algorithms are utilized to improve the reliability of motion vectors. This format converter has been developed using field programmable gate arrays, digital signal processors and specially designed VLSI-chips for reduction of hardware amount. These VLSI- chips have been realized as semicustom and fullcustom chips. Besides employment within the format converter they are suitable for various applications in video processing.

Date Published: 16 September 1994
PDF: 9 pages
Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994); doi: 10.1117/12.185946

Published in SPIE Proceedings Vol. 2308:
Visual Communications and Image Processing '94
Aggelos K. Katsaggelos, Editor(s)