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Proceedings Paper

Low-power design of wavelet processors
Author(s): Yi Kang; Belle W. Y. Wei; Teresa H.-Y. Meng
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Paper Abstract

This paper describes a VLSI architecture for low-power image compression applications. It implements a block-based wavelet transform with emphasis on minimal memory requirements, power consumption, and compression performance. The blocked transform partitions the original image into 16 X 16 data blocks with repeated boundary pixels for edge smoothing. Each block undergoes four octaves of 2D wavelet decomposition, and results in 13 subbands. The first octave uses Daubechies-4 transform, and the second, third, and fourth use Haar functions. The architecture consists of four 8-bit X 7-bit multiplier and accumulator units and one 13-bit adder. It implements 2D wavelet transforms directly with minimal memory and a small chip area. At 60 MHz, it processes a 512 X 512 gray-scale image in 23 ms and 18 ms for forward and inverse transforms respectively, satisfying the full-motion video requirement of 30 frames per second.

Paper Details

Date Published: 16 September 1994
PDF: 7 pages
Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994); doi: 10.1117/12.185936
Show Author Affiliations
Yi Kang, Specom Inc. (United States)
Belle W. Y. Wei, Stanford Univ. (United States)
Teresa H.-Y. Meng, Stanford Univ. (United States)

Published in SPIE Proceedings Vol. 2308:
Visual Communications and Image Processing '94
Aggelos K. Katsaggelos, Editor(s)

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