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Proceedings Paper

Circuit design: emphasis on mask design and specification
Author(s): Hoyoung Kang; Chang-Jin Sohn; Woo-Sung Han; Young-Bum Koh; Moon-Yong Lee
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Paper Abstract

In the past, the wafer pattern dimension was same as the mask pattern dimension because 1x exposure tool was widely used until 64KDRAM era. With the introduction of 5x stepper, required mask pattern dimension became five times larger and writing area was reduced as much.

Recently, 64MDRAM and 256MDRAM whose feature sizes are smaller than 0.4μm and required patterning area is wider, require finer geometry and larger patterning area especially considering 4x exposure tools.

In order to lighten both lithography and mask process burdens, new design techniques are considered for new DRAM generations such as COB (capacitor on bit line), IDB(inter-digit bit line) and SWD(split word line driver).

Especially with the improvement of lithography technology using techniques such as phase shift mask and off axis illumination, optical proximity effect is unavoidable by nature. In order to correct this proximity effect, square cornered fine patterns well below the resolution limit of exposure tool are desirable.

In this review, detailed discussion of new technology will not be discussed but related mask making requirement will be discussed instead.

Paper Details

Date Published: 1 January 1994
PDF: 19 pages
Proc. SPIE 10273, 64-to 256-Megabit Reticle Generation: Technology Requirements and Approaches: A Critical Review, 1027303 (1 January 1994); doi: 10.1117/12.177436
Show Author Affiliations
Hoyoung Kang, Samsung Electronics Co. Ltd. (United States)
Chang-Jin Sohn, Samsung Electronics Co. Ltd. (South Korea)
Woo-Sung Han, Samsung Electronics Co. Ltd. (South Korea)
Young-Bum Koh, Samsung Electronics Co. Ltd. (South Korea)
Moon-Yong Lee, Samsung Electronics Co. Ltd. (South Korea)

Published in SPIE Proceedings Vol. 10273:
64-to 256-Megabit Reticle Generation: Technology Requirements and Approaches: A Critical Review
Gregory K. Hearn, Editor(s)

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