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Proceedings Paper

JPEG image compression hardware implementation with extensions for fixed-rate and compressed-image editing applications
Author(s): Martin P. Boliek; James D. Allen; Tadanori Ryu; Yutaka Sato; Jun-ichi Hara
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Paper Abstract

This paper describes a new high speed image compression hardware implementation which, in addition to implementing the JPEG baseline system, can be used in fixed-rate compression systems and in systems that allow editing of compressed images. High speed (CCIR 601 resolution at 30 frames/second) and small silicon size are achieved by using a unique parameterized orthogonal transform. This implementation is compatible with the DCT, yet requires no additional multiplications. Also described here is a system that uses a dynamic quantization scalar circuit to achieve fixed-rate compression and a system that utilizes the `static coefficient DPCM' feature to compress and decompress regions of interest within an image for editing or viewing.

Paper Details

Date Published: 2 May 1994
PDF: 10 pages
Proc. SPIE 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies, (2 May 1994); doi: 10.1117/12.174954
Show Author Affiliations
Martin P. Boliek, Ricoh California Research Ctr. (United States)
James D. Allen, Ricoh California Research Ctr. (United States)
Tadanori Ryu, Ricoh Co., Ltd. (Japan)
Yutaka Sato, Ricoh Co., Ltd. (Japan)
Jun-ichi Hara, Ricoh Co., Ltd. (Japan)

Published in SPIE Proceedings Vol. 2187:
Digital Video Compression on Personal Computers: Algorithms and Technologies
Arturo A. Rodriguez, Editor(s)

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