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Proceedings Paper

Strategies for characterizing and optimizing overlay metrology on extremely difficult layers
Author(s): Paul R. Anderson; Robert J. Monteverde
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Paper Abstract

Overlay budgets for advanced products are in the range of 100 to 150 nm; mean plus 3 sigma. It is crucial that the metrology tool contribute a minimal amount of error since the majority of the overlay specification is used up by the stepper errors. Most of the newer tools available today have no problem in achieving this criterion, even at these tight specifications. However, certain semiconductor processes produce overlay targets that are very difficult to measure such as grainy metal, tungsten plugged vias, and well planarized substrates. These substrates can be, roughly, grouped into two categories of `low contrast' and `distorted targets.' In the case of the low contrast targets, the signal to noise ratio is very low and the metrology tool has difficulty in identifying the actual target. Distorted targets can be measured but appear different to the metrology tool from one location to the other due to random distortions of the target edges thus producing erroneous measurements.

Paper Details

Date Published: 1 May 1994
PDF: 6 pages
Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); doi: 10.1117/12.174140
Show Author Affiliations
Paul R. Anderson, Motorola (United States)
Robert J. Monteverde, KLA Instruments Corp. (United States)

Published in SPIE Proceedings Vol. 2196:
Integrated Circuit Metrology, Inspection, and Process Control VIII
Marylyn Hoy Bennett, Editor(s)

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