We describe an interline CCD imaging array which features high-speed, on-chip, parallel A/D conversion. In addition, we present test results from fabricated devices. The imaging chip was fabricated through MOSIS in a double-poly 2.0 micrometers CCD/CMOS technology on a chip with total area 2.25 mm X 2.22 mm. The chip is composed of a 28 X 39 pixel, interline imaging array, and a bank of 39 single-slope CCD/CMOS A/D converters; the converters function in parallel to achieve effective high-speed A/D conversion. Chip output is a stream of 8-bit digital data in which each 8-bit value corresponds to the light level at a pixel. Once an image has been captured, a set of parallel CCD shift registers transfer the data one column at a time to the parallel A/D converters. The analog data from each column is then converted in parallel and the resulting digital values are read out serially.

Date Published: 1 May 1994
PDF: 10 pages
Proc. SPIE 2172, Charge-Coupled Devices and Solid State Optical Sensors IV, (1 May 1994); doi: 10.1117/12.172772

Published in SPIE Proceedings Vol. 2172:
Charge-Coupled Devices and Solid State Optical Sensors IV
Morley M. Blouke, Editor(s)