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Proceedings Paper

Spin on glass (SOG)-based planarization scheme compatible with a stacked via multilevel metal process
Author(s): Maurizio Bacchetta; Laura Bacci; Nadia Iazzi; I. Liles; Luca Zanotti
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Paper Abstract

In this work an inter-metal dielectric (IMD) planarization process, developed for multimetal submicron technology devices, is presented. The feasibility to build up to five metal levels with W blanket-etch back stacked plug interconnections is shown, using a new Spin On Glass (SOG) material and a semi-integrated planarization process in which a bake, a SOG Partial Etch Back (PEB), and a TEOS oxide cap layer deposition are done sequentially in the same cluster tool. The presented planarization process allows a very low over-etch for the W etch back step at each plug level and, consequently, a quite good control of the plug recession as required by stacked vias. This new process has effectively extended the life of an existing SOG Partial Etch Back process already established on existing equipment. Planarization process performances have been tested on an advanced triple metal device with stacked W plugs and on a test device with five metal levels with various metal pitches. Process results are presented in terms of defect density, repeatability, and electrical tests on stacked via chain structures.

Paper Details

Date Published: 15 September 1993
PDF: 13 pages
Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); doi: 10.1117/12.156534
Show Author Affiliations
Maurizio Bacchetta, SGS-Thomson Microelectronics (Italy)
Laura Bacci, SGS-Thomson Microelectronics (Italy)
Nadia Iazzi, SGS-Thomson Microelectronics (Italy)
I. Liles, SGS-Thomson Microelectronics (Italy)
Luca Zanotti, SGS-Thomson Microelectronics (Italy)

Published in SPIE Proceedings Vol. 2090:
Multilevel Interconnection: Issues That Impact Competitiveness
Hoang Huy Hoang; Ron Schutz; Joseph B. Bernstein; Barbara Vasquez, Editor(s)

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