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Proceedings Paper

Technological limitations in submicron on-chip interconnect
Author(s): Soo-Young Oh; Keh-Jeng Chang; Norman Chang; Ken Lee; John L. Moll
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Paper Abstract

The trend of the performance degradations, noise and reliability issues and their potential solutions are analyzed for the submicron ULSI interconnect lines. To analyze these submicron interconnect lines, a new paradigm (HIVE) for fast and accurate 2-D and 3-D interconnect capacitances and resistances calculation is developed. The analysis, using these interconnect parameters for HIVE, shows that a copper (Cu) line will improve the electromigrations, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improve the interconnect delay and electromigration, but it increases the cost of system packaging. The optimum approach will be the combination of additional layers of non-scaled metal lines in a higher level, low permittivity interlevel dielectric, and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.

Paper Details

Date Published: 21 May 1993
PDF: 8 pages
Proc. SPIE 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations, (21 May 1993); doi: 10.1117/12.145475
Show Author Affiliations
Soo-Young Oh, Hewlett-Packard Co. (United States)
Keh-Jeng Chang, Hewlett-Packard Co. (United States)
Norman Chang, Hewlett-Packard Co. (United States)
Ken Lee, Hewlett-Packard Co. (United States)
John L. Moll, Hewlett-Packard Co. (United States)

Published in SPIE Proceedings Vol. 1805:
Submicrometer Metallization: Challenges, Opportunities, and Limitations
Thomas Kwok; Takamaro Kikkawa; Krishna Shenai, Editor(s)

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