Share Email Print

Proceedings Paper

VHDL as a specification language for high-level synthesis system
Author(s): Wojciech Sakowski; Miroslaw Ossysek; Benedykt Nowak
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The paper presents the results of research work carried out as an introductory effort toward development of a high level synthesis system. The restrictions imposed on the behavioral specifications and the language extensions provided to control the synthesis process are discussed. The internal machine representation of the initial specification is presented.

Paper Details

Date Published: 1 August 1992
PDF: 10 pages
Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); doi: 10.1117/12.141062
Show Author Affiliations
Wojciech Sakowski, Silesian Technical Univ. (Poland)
Miroslaw Ossysek, Silesian Technical Univ. (Poland)
Benedykt Nowak, Silesian Technical Univ. (Poland)

Published in SPIE Proceedings Vol. 1783:
International Conference of Microelectronics: Microelectronics '92
Andrzej Sowinski; Jan Grzybowski; Witold T. Kucharski; Ryszard S. Romaniuk, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?