As minimum feature sizes are reduced in MOS silicon devices, dielectric breakdown continues to pose a formidable challenge. A more complete understanding of the failure mechanism which induces oxide rupture has become an absolute necessity in order to meet the advancing yield and reliability requirements of today's complex integrated structures. This paper will present an interesting insight into the nature of dielectric breakdown in MOS transistors produced from a novel cross-sectioning TEM sample preparation method using a focused ion beam tool. By using deductive failure analysis, it was possible to determine the location of the leakage within a 1000 angstroms portion of the transfer gate of a one megabit DRAM. Once localized, a creative combination of conventional glass lapping and focused ion beam techniques were used to produce the thin TEM slice which contained the oxide breakdown. An image of the breakdown was then obtained on a 200 keV TEM. Interestingly, the image revealed that the origin of the breakdown was associated with imperfections in the form of voids in the surface of the silicon substrate. These results proved to be consistent over multiple samples. In this paper a complete description of these images will be presented along with possible theories describing the fundamental origin of these defects.

Date Published: 14 January 1993
PDF: 8 pages
Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993); doi: 10.1117/12.139343

Published in SPIE Proceedings Vol. 1802:
Microelectronics Manufacturing and Reliability
Barbara Vasquez; Anant G. Sabnis; Kenneth P. MacWilliams; Jason C.S. Woo, Editor(s)