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Proceedings Paper

High-speed test station for solid state imagers
Author(s): George J. Yates; Kevin L. Albright; Bojan T. Turko
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Paper Abstract

A PC-based programmable solid-state imager test station has been designed and is in final development phases. It is designed to provide a flexible universal high-speed platform for evaluation of different imager designs and formats including various multiport configurations. The system provides drive and acquisition circuitry and components to allow electro-optic characterization of imagers as a function of pixel readout rate. The data are scan-converted to RS-170 format for analysis. The system's functional capabilities and performance are presented. Examples of program code to generate three phase clocks for an 8-port Frame Transfer EEV CCD are included. A sampling of preliminary results obtained from variable rate clocking of this imager are discussed.

Paper Details

Date Published: 19 January 1993
PDF: 12 pages
Proc. SPIE 1757, Ultrahigh- and High-Speed Photography, Videography, and Photonics, (19 January 1993); doi: 10.1117/12.139135
Show Author Affiliations
George J. Yates, Los Alamos National Lab. (United States)
Kevin L. Albright, Los Alamos National Lab. (United States)
Bojan T. Turko, Lawrence Berkeley Lab. (United States)

Published in SPIE Proceedings Vol. 1757:
Ultrahigh- and High-Speed Photography, Videography, and Photonics
Donald R. Snyder, Editor(s)

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