Almost any frame grabber system has a special controller circuit to transfer data from the video analog to digital converter (ADC) to the system memory. This controller which normally includes a locked phase loop (PLL) and several counters has to fulfill three main functions: the generation of a pixel clock synchronized with the incoming video signal the command of the ADC and memory addressing for the storage of the digitized video. This paper shows how a digital signal processor (DSP) can simplify the design of a video acquisition system by reading the video ADC and writing to its memory at video rates. An example is given with the TM5320C30 processor which supports simultaneous read and write operations on its two external buses. In the case of the CCJR 601 video format the processor runs at 27 MHz. Modern versions of the TMS32OC3O running at as fast as 40 MHz can acquire up to 1066 samples per line. Also the 32-bit wide buses of the processor allows colour acquisition using this technique. In order to build a so simple circuit the DSP needs to be synchronized to the incoming video signal which can be neatly done by using the TMS32OC3O internal timer as part of the PLL. By changing the programming of the internal timer any video format can be grabbed. In addition the DSP can be used as a powerful image

Date Published: 12 August 1992
PDF: 5 pages
Proc. SPIE 1656, High-Resolution Sensors and Hybrid Systems, (12 August 1992); doi: 10.1117/12.135918

Published in SPIE Proceedings Vol. 1656:
High-Resolution Sensors and Hybrid Systems
Morley M. Blouke; Winchyi Chang; Laurence J. Thorpe; Rajinder P. Khosla, Editor(s)