This paper details the design of a DSP chip set for NOVI-III, a massively parallel digital signal processing system for super high definition (SHD) image coding. In the first step, achieving real-time SHD image processing, we implemented the JPEG coding algorithm on the highly parallel DSP system called NOVI-II HiPIPE, and evaluated its processing performance. The result shows that a real-time CODEC must have an average computational performance of over 100 GFlops (floating point operations) to process SHD motion images. Based on our experience of still SHD image coding, a new DSP chip set is being designed for NOVI-III. The chip set consists of three main chips. The first chip is a vector processor that, in its original form, had a peak performance of 120 MFlops. It is being redesigned to achieve a peak performance of 540 MFlops with 0.5 micrometers fabrication technology. Second is an intercommunication network switch that has six 400 Mbps data links. Third is a RISC type DSP core which controls the vector processor, communication switch and internal memories. This DSP core also has a special function that efficiently performs the bit operations required by the Huffman coding process.

Date Published: 1 November 1992
PDF: 12 pages
Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); doi: 10.1117/12.131430

Published in SPIE Proceedings Vol. 1818:
Visual Communications and Image Processing '92
Petros Maragos, Editor(s)