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Proceedings Paper

VLSI Reed-Solomon decoder
Author(s): Yong Hwan Kim; Young Mo Chung; Sang Uk Lee
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Paper Abstract

In this paper, a VLSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provides both erasure and error correcting capability. In order to reduce the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed. And the overall architecture features parallel and pipelined structure, making a real time decoding possible. It is shown that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the architecture based on the recursive Euclid algorithm.

Paper Details

Date Published: 1 November 1992
PDF: 12 pages
Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); doi: 10.1117/12.131377
Show Author Affiliations
Yong Hwan Kim, Seoul National Univ. (South Korea)
Young Mo Chung, Seoul National Univ. (South Korea)
Sang Uk Lee, Seoul National Univ. (South Korea)

Published in SPIE Proceedings Vol. 1818:
Visual Communications and Image Processing '92
Petros Maragos, Editor(s)

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