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Proceedings Paper

Efficient bit-level systolic arrays for QMF banks
Author(s): Chia-Wen Lin; Yung-Chang Chen; Chin-Liang Wang
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Paper Abstract

In this paper, various systolic arrays are proposed for the application to quadrature mirror filter (QMF) banks. A word-level systolic array is firstly presented to realize QMF banks. It is subsequently refined to bit-level array with bit-parallel arithmetic via the well-known two-level pipelining techniques and is then converted to bit-serial form by using the bit-serial inner product array proposed by Wang et al.. By applying the polyphase representation as well as fully utilizing the special relations among QMFs', aside from the memory cost, the whole filter bank can be constructed by using only about one half of the hardware expense of a prototype filter. In comparison with the direct realization using polyphase representation, the number of the systolic multiplier-accumulators (SMAs) required for our architecture is halved. Thus, both the chip area and transistor-count are reduced. As a result, with today's commercial CMOS technology, the whole filter bank can be implemented within a single-chip for various video applications.

Paper Details

Date Published: 1 November 1992
PDF: 12 pages
Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); doi: 10.1117/12.131374
Show Author Affiliations
Chia-Wen Lin, National Tsing Hua Univ. (Taiwan)
Yung-Chang Chen, National Tsing Hua Univ. (Taiwan)
Chin-Liang Wang, National Tsing Hua Univ. (Taiwan)

Published in SPIE Proceedings Vol. 1818:
Visual Communications and Image Processing '92
Petros Maragos, Editor(s)

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