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Spie Press Book

Copper Interconnect Technology
Author(s): Christoph Steinbruchel; Barry L. Chin
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Book Description

Copper interconnect technology is expected to be a key component in the quest to create more powerful CPUs and memory chips. This text examines the role of copper in future interconnects, presents the range of problems involved, and explains how the solutions are being found.

Book Details

Date Published: 30 January 2001
Pages: 134
ISBN: 9780819438973
Volume: TT46

Table of Contents
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Introduction / 1
1. Interconnect issues / 3
1.1 Overview / 3
1.2 Materials requirements / 6
1.3 Materials options / 10
1.4 Multilevel interconnect fabrication / 12
2. Copper deposition / 16
2.1 Overview / 16
2.2 Chemical deposition methods for copper / 16
2.2.1 Chemical vapor deposition (CVD) / 17
2.2.2 Electrochemical plating (ECP) / 19
2.3 Physical deposition methods for copper / 21
2.3.1 Collimated and long-throw sputter deposition / 22
2.3.2 Ionized physical vapor deposition (IPVD) / 23
3. Copper patterning / 26
3.1 Overview / 26
3.2 Subtractive copper patterning / 27
3.2.1 Reactive ion etching (RIE) of copper / 28
3.2.2 Etching of copper in high-density plasmas (MI, ECR, ICP) / 29
3.2.3 Radiation-enhanced RIE of copper / 30
3.3 Additive copper patterning by chemical-mechanical polishing (CMP) / 31
4. Interlayer dielectrics / 34
4.1 Silicate-based ILDs / 35
4.1.1 Undoped Si oxides / 35 Nanoporous silica / 35 Silica with air gaps/ 37
4.1.2 Doped Si oxides / 38 H-doped oxide: Hydrogen silsesquioxane / 38 F-doped oxide / 39 C-doped oxide / 41
4.2 Organic polymer-based ILDs / 43
4.2.1 Non-fluorinated organic polymers / 43 Parylene-n [poly(p-xylylene)] / 43 Benzocyclobutene (BCB, Cyclotene 501) / 44 FLARE 2.0 / 44 SiLK / 44
4.2.2 Fluorinated organic polymers / 45 Parylene-f [poly(tetrafluoro-p-xylylene)] / 43 Perfluoro-cyclobutane (PFCB) / 46 FLARE 1.0 and 1.51 / 46 Fluorinated amorphous carbon (a-C:F) / 46 Teflon (PTFE) / 47
4.3 Patterning of ILDs / 48
4.3.1 Overview /49
4.3.2 Patterning of silicate-based ILD's / 51
4.3.3 Patterning of organic polymeric ILDs / 53
4.3.4 Etching dual-damascene structures into the ILD / 54
4.3.5 Via cleaning / 55
4.3.6 Planarization of low-k ILDs by CMP/ 56
5. Cu/ILD barriers / 60
5.1 Cu/undoped-SiO2 barriers / 62
5.2 Cu/doped-SiO2 barriers / 64
5.3 Cu/polymer barriers / 65
6. Current practice / 68
6.1 Overview / 68
6.2 Pre-clean / 68
6.3 Barrier layers / 69
6.4 Copper fill methods / 70
6.5 Future directions / 74
Index / 78


The semiconductor industry is continuing its quest to create ever more powerful CPU and memory chips.1 These efforts are focused principally in two areas. On one hand, the speed of individual devices is increased through the continual education of the minimum size of device features. Along with this goes a corresponding increase in device density on the chip. On the other hand, in order to take advantage of increased device speeds, one needs to connect individual devices into circuits using increasingly complex interconnect schemes. These now involve multiplayer structures made up of several levels of metal wiring separated by an interlayer dielectric (ILD). Efforts in both of these areas are supported by more and more sophisticated device and circuit design.

The exact nature of the trade-off between individual device and interconnect performance depends on details of the circuit architecture. However, it is now generally recognized that the overall circuit performance is going to be dominated by the efficiency with which devices are connected rather than by the speed of the individual devices. From the materials point of view, a better interconnect efficiency may be achieved with various new materials combinations for the metal and the interlayer dielectric (ILD). It is now becoming apparent that a major component of improved interconnect performance will consist in replacing aluminum, the previous metal of choice, with copper.

Several companies announced recently that they have been successful in fabricating ultralarge-scale integrated (ULSI) circuits using Cu.2 5 IBM 2 was first to publish pictures showing interconnect structures with six levels of Cu metal (M1-M6, see Figs. 1 and 2). Some of the features of the announced Cu processes are given below. The IBM process has been described in detail in Ref. [3].

IBM:4a CMOS process (Cu with SiO2); M1 contacted pitch 0.63 _m, M2-M6 contacted pitch 0.91 _m, local tungsten interconnects, gate length 0.20 _m, SRAM cell size 6.8 _m 2 .

Motorola:5 CMOS process (Cu with SiO2); M1 pitch 0.63 _m, M6 pitch 1.62 _m, gate length 0.15 _m, SRAM cell size 7.6 _m 2 .

Texas Instruments:6 Interconnect tests structures with 0.3 _m Cu lines embedded in xerogel, capped with silicon nitride and silicon oxide.

Very recently, IBM reported on two technologies involving Cu and an ILD with lower dielectric constant than silicon dioxide. In the first paper,4b the integration of fluorine-doped oxide with Cu for the 0.18-_m node has been described. In the second paper,4c the application of Cu and an organic material as the ILD for the 0.13-_m technology node has been demonstrated. (For further details see Section 7.) The purpose of this book is to present a tutorial overview of the issues involved in implementing the use of copper in future interconnect technologies. We will attempt to give the reader an appreciation of the range of problems involved and the avenues along which solutions to these problems are being sought. With this focus in mind, we will not try to deal exhaustively with all the technical issues in every area covered. This would be beyond the scope of this book. Rather, we will provide representative examples of the most important technical approaches being pursued and references to more in-depth information elsewhere. In order to put our arguments in perspective, it will be worth taking note of Ref. [7], which contains an extensive discussion of previous, aluminum-based interconnect technologies as well as early work in copper technology.

The organization of the book is as follows: We start with a brief description of the status, major issues, and materials options for interconnect technologies. Next we illustrate in general terms different approaches to the fabrication of multilayer interconnect structures, with particular emphasis on how to create patterned multilayers. This includes a comparison of subtractive patterning, as used with Al metallization, and damascene patterning, as used with Cu metallization. We then give a general discussion of Cu deposition and patterning, interlayer dielectrics, Cu diffusion barriers and passivation, and Cu/barrier/ILD issues, with a focus on scientific fundamentals, potential process alternatives, and future options. We conclude with a detailed description of the preferred approaches and technological practices being implemented at this time

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