Sage Design Automation – an Applied Materials company

SIGN IN: Sign in to see additional content and features
Sign in

About

Sage Design Automation, an Applied Materials company, provides unique solutions for Design Enablement as well as rapid technology path-finding for Materials to Systems Co-optimization™. The Sage-DA EDA portfolio accelerates MSCO™ iterations by an order of magnitude, thus enabling many more combinations of different materials, process and transistor device configurations for a thorough analysis of their interdependencies and PPAC trade-offs at a design and system level.
Show full description +

Contact

Sage Design Automation – an Applied Materials company
3050 Bowers Avenue
Santa Clara, CA
United States
95054
Website: www.sage-da.com

Connect with a representative

Reach out to start a live chat conversation with a company representative. If a company representative is not available at the time of your request, you may choose to have an email delivered to them.

Company video

Sign in to view the video

Request information

Want to send this Exhibitor an email?
MUST be signed into SPIE account AND registered for the event.

Announcements

16 February 2021
MSCO flow for logic – paper presentation
Applied Materials will present a case study of an automated Standard Cell Library generation for use in Materials to Systems Co-Optimization flow. The paper examines the impact of advanced materials, process and design rules on complex Standard Cells and explores innovative Standard Cell architectural choices at the N3 technology node. The flow uses SLiC for automated generation of Standard Cells, enabling rapid iterations and analysis of multiple design and process options. The paper will be presented in Design-Technology Co-Optimization XV conference, Session 9, Paper 11614-36 by Maarten Berkens.
16 February 2021
MSCO flow for memory – paper presentation
Applied Materials will present a framework that extends Materials to Systems Co-Optimization (MSCO) modeling to memory array simulations. This paper describes a methodology that builds models from materials and process, through devices, memory cells and to full memory arrays, and its application to an embedded SARM array in a N3 logic technology. The paper will be presented in Design-Technology Co-Optimization XV conference, Session 4, Paper 11614-14, by Ashish Pal.
PREMIUM CONTENT
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?
close_icon_gray