The processing power available in current video graphics cards is approaching super computer levels. In the past two years the processing power in these cards has quadrupled. State-of-the-art graphical processing units (GPU) boast of computational performance in the range of 1.4 trillion floating point operations per second (1.4 Teraflops). This processing power is readily accessible to the scientific community at a relatively small cost. High level programming languages are now available that give access to the internal architecture of the graphics card allowing greater algorithm optimization. This research takes computationally expensive portions of an image-based iris identification algorithm and hosts it on a GPU using the C++ compatible CUDA language. The selected segmentation algorithm uses basic image processing techniques such as image inversion, value squaring, thresholding, dilation, erosion and the computationally intensive local kurtosis calculation (fourth standardized moment) and circular Hough transform. Strengths and limitations of the GPU Single Instruction Multiple Data architecture are discussed. The primary source of the graphical processing power, the multiple processing elements and layered memory system, are discussed in detail. Actual memory access and instruction execution times are provided. Impressive acceleration results were obtained. The iris segmentation algorithm was accelerated by a factor of 150 over the highly optimized C++ version hosted on the computer's central processing unit. Some parts of the algorithm ran at speeds that were over 400 times faster than their C++ counterpart. CUDA programming details and code samples are presented as part of the acceleration discussion.

Distribution of computer vision tasks in parallel environments is essential considering the increasing demand for computational resources to accomplish advanced visual processing tasks. Thus, a consistent and efficient but yet convenient system for parallel computer vision, and in fact also realtime actuator control is proposed. The system implements the multi-agent paradigm and a blackboard information storage. This, in combination with a generic interface for hardware abstraction and integration of external software components, is setup on basis of the message passing interface, which is the de facto standard for HPC environments and hence provides support for a large variety of platforms and has a huge user pool. The system furthermore allows for data- and task-parallel processing, and supports both synchronous communication, as data exchange can be triggered by events, and asynchronous communication, as data can be polled, strategies. Also, by duplication of processing units (agents) redundant processing is possible to achieve greater robustness. As the system automatically distributes the agents to available resources, and a monitoring concept allows for combination of tasks and their composition to complex processes, it is very easy to develop vision / robotics applications quickly. Thus, for evaluation multiple vision based applications have already been implemented, e.g. an evolutionary approach for learning visual saliency features, or a parallel active perception system for robotic recognition and handling of limp objects.

HP's digital printing presses consume a tremendous amount of data. The architectures of the Digital Front Ends (DFEs) that feed these large, very fast presses have evolved from basic, single-RIP (Raster Image Processor) systems to multi-rack, distributed systems that can take a PDF file and deliver data in excess of 1.1 Gigapixels per second to keep the presses printing at 2500+ pages per minute. This paper highlights some of the more interesting parallelism features of our DFE architecture. The high-performance architecture developed over the last 5+ years can scale up to HP's largest digital press, out to multiple mid-range presses, and down into a very low-cost single box deployment for low-end devices as appropriate. Principles of parallelism pervade every aspect of the architecture, from the lowest-level elements of jobs to parallel imaging pipelines that feed multiple presses. From cores to threads to arrays to network teams to distributed machines, we use a systematic approach to move bottlenecks. The ultimate goals of these efforts are: to take the best advantage of the prevailing hardware options at our disposal; to reduce power consumption and cooling requirements; and to ultimately reduce the cost of the solution to our customers.

Advances in the image processing field have brought new methods which are able to perform complex tasks robustly. However, in order to meet constraints on functionality and reliability, imaging application developers commonly design complex algorithms with many parameters which need to be finely tuned for each particular environment. The best approach to tune these algorithms is to use an automatic training method, but a major issue arises when designing this kind of training method: the computational cost. The execution of the training method can be completely prohibitive, even in powerful machines. The same problem shows up when designing testing procedures. This work presents methods to train and test complex image processing algorithms within parallel execution environments. The approach proposed in this work is to use existing resources, in offices or laboratories, rather than expensive clusters. These resources are typically non-dedicated, heterogeneous and unreliable. The proposed methods have been designed to deal with all these issues. Two different methods are proposed: intelligent training based on genetic algorithms and PVM, and a full factorial design based on grid computing which can be used for training or testing. These methods are capable of harnessing the available computational power resources, giving more work to more powerful machines, and also taking its unreliable nature into account. Both methods have been tested using real applications.

Printing systems composed of multiple, interconnected marking engines (MEs) provide many potential advantages compared with ad hoc single engine designs. Tightly integrated multi-ME systems enable, for example, near optimal system utilization and document throughput through multi-threaded job production. Composable printing systems allow reconfigurability to match user needs and redundancy to support high reliability. The work presented here describes a system of four MEs linked by a paper path that has a deep level of modularity. The paper path consists of a regular grid populated by a small number of module types - nip modules to provide bidirectional sheet motion and two types of directors for static and dynamic definition of path topology. Each module is capable of acting, sensing, computing and communicating. Modules including MEs, are hot-swappable, and the system is capable of auto-configuration. Real-time planning and control software, like the hardware, is designed to be modular, distributed, reconfigurable and scalable. The system can handle exceptions, such as sheet jams, while maintaining (reduced) throughput.

Many image recognition tasks are well-suited to parallel processing. The most obvious example is that many imaging tasks require the analysis of multiple images. From this standpoint, then, parallel processing need be no more complicated than assigning individual images to individual processors. However, there are three less trivial categories of parallel processing that will be considered in this paper: parallel processing (1) by task; (2) by image region; and (3) by meta-algorithm. Parallel processing by task allows the assignment of multiple workflows-as diverse as optical character recognition [OCR], document classification and barcode reading-to parallel pipelines. This can substantially decrease time to completion for the document tasks. For this approach, each parallel pipeline is generally performing a different task. Parallel processing by image region allows a larger imaging task to be sub-divided into a set of parallel pipelines, each performing the same task but on a different data set. This type of image analysis is readily addressed by a map-reduce approach. Examples include document skew detection and multiple face detection and tracking. Finally, parallel processing by meta-algorithm allows different algorithms to be deployed on the same image simultaneously. This approach may result in improved accuracy.

In recent years we assist to an increase of interest in using texture features in industrial applications. For this type of applications, real time processing is an important issue. Different approaches are available to solve this problem: DSP, FPGA, parallel systems, etc. More recently a research community became interested in GPU available in commercial graphic cards with the objective of using the processing power of the GPU in order to accelerate general purpose processing. In this work we present the use of GPGPU for building a framework for parallel real time texture analysis in computer vision. The following techniques were developed: LBP, LTP, Laws, Gabor and GLCM. We used NVIDIA CUDA technology for developing the proposed algorithms. GPU performance is compared to CPU using MMX-SSE optimizations and Multicore parallel programming. The experimental results show an important increase in the performance of the proposed algorithms when GPGPU is used particularly for larger images.

<p> Zernike polynomials are a well known set of functions that find many applications in image or pattern characterization because they allow to construct shape descriptors that are invariant against translations, rotations or scale changes. The concepts behind them can be extended to higher dimension spaces, making them also fit to describe volumetric data. They have been less used than their properties might suggest due to their high computational cost. </p><p> We present a parallel implementation of 3D Zernike moments analysis, written in C with CUDA extensions, which makes it practical to employ Zernike descriptors in interactive applications, yielding a performance of several frames per second in voxel datasets about 200^3 in size. </p><p> In our contribution, we describe the challenges of implementing 3D Zernike analysis in a GPGPU. These include how to deal with numerical inaccuracies, due to the high precision demands of the algorithm, or how to deal with the high volume of input data so that it does not become a bottleneck for the system. </p><p> Our GPU-based implementation runs about ten times faster than our previous CPU-based one. </p>

This paper addresses the problem of airport detection and runway segmentation in satellite images with complex background clutter. To this ends, we propose a novel ensemble learning based parallel runway segmentation algorithm. The contributions of our work can be summarized as follows: (a) we propose the concept of priority direction region growing. (b) We introduce the Bresenham's line generation algorithm into our segmentation task. (c) we adopt a two-stage strategy to better segment the regions corresponding to the airport runway by applying traditional region growing method and our priority directions (two orthogonal directions in our problem) growing method. (d) In our runway segmentation algorithm, ensemble-learning strategy is used to combine the growing results of each line segment. In addition, those thin branches, which have significantly different width, are eliminated. To evaluate the effectiveness of our algorithm, extensive simulations are carried out on the testing images obtained from Google Map. Our experimental results show that our algorithm can effectively and efficiently segmented the airport region, and generate very neat boundaries of the runways, and have great superiority over the state-of-the-art methods.

This paper discusses the experimental results of our visualization model for data extracted from sensors. We have to find the faster and more efficient method to produce a real time rendering visualization for a large amount of data. We develop visualization methods to monitor temperature variance of a data center. Sensors are placed on three layers and do not cover all the room. We use particle paradigm to interpolate data sensors, as presented in \cite{Latta2004}. Particles model the "space" in the room, as stated by the Industry Foundation Classes (IFC) model, a standard building semantic model. In this work we make a partition of the particle set using two mathematical methods: Delaunay triangulation and Vorono\"\i\ cells. Avis and Bhattacharya present these algorithms in \cite{Avis1983} . Particles carry information of the room temperature, and display the evolution of temperature in time. To locate and update particles data we have defined a computational cost function. To solve this function in an efficient way, we use a client server paradigm \cite{Kapferer2008}. Server computes data, client display this data in a virtual screen composed from four video projectors in stereoscopic view. This paper is organized as follows. The first part presents related solutions used to visualize large flow of data. The second part presents our different platforms and methods used, which have been evaluated in order to determine the better solution for the task proposed. The benchmark use the computational function of our algorithm, it was based on located particles compared to sensors and on update of particles value. Figure \ref{fig-10} and \ref{fig-11} illustrate the inclusion method using ray tracing, each particle is tested on the nearest tetrahedron. The benchmark was done on a personal computer using CPU, multi core programming. However, real time rendering is hard to have. This work is performed in collaboration with IBM Montpellier, and within this collaboration, our work can be improved on High Performance Computer and on a hybrid CPU, GPU server. The first method is commonly used in data visualization (astronomy, physic, etc.) and the second one is growing in computer science. With this other different platform we want to have a real time rendering of our large data flow.

In this paper, a highly effective and efficient ensemble learning-based parallel algorithm for impulse noise detection is proposed. The contribution of this paper is three-fold. First, a novel intensity homogeneity metric, which has very powerful discriminative ability that has been proven, is proposed. Second, this proposed algorithm has high parallelism in feature extraction stage, classifier training and testing stage. Finally, instead of manually tuning the thresholds for each feature as most of the works in this research area do, Random Forests (RF) is used to make decision since it has been demonstrated to own better generalization ability and performance comparable to SVMs in classification problem. Another important reason why RF is adopted is that it has natural parallelism structure and very significant performance advantage (e.g. the overhead of training and testing the model) over other popular classifiers e.g. SVMs. To the best of our knowledge, this is the first time that the ensemble learning strategies have been used in the area of switching median filtering. Extensive simulations are carried out on eight most common standard testing images. The experimental results show that our algorithm achieves zero-miss detection result while keeping the false alarm rate at a rather low level, and has great superiority over other state-of-the-art methods.

Tetrahedral interpolation is commonly used to implement continuous color space conversions from sparse 3D and 4D lookup tables. We investigate the implementation and optimization of tetrahedral interpolation algorithms for GPUs, and compare to the best known CPU implementations. We show that a $350 NVIDIA GTX-470 GPU is 4x faster than a $1000 Intel Core i7 980X CPU for 3D interpolation, and 16x faster for 4D interpolation. Performance-relevant GPU attributes are explored including thread scheduling, local memory characteristics, global memory hierarchy, and cache behaviors. We consider existing tetrahedral interpolation algorithms and tune based on the structure and branching capabilities of current GPUs. Global memory performance is improved by reordering and expanding the lookup table to ensure optimal access behaviors. Per multiprocessor local memory is exploited to implement optimally coalesced global memory accesses, and local memory addressing is optimized to minimize bank conflicts. We explore the impacts of lookup table density upon computation and memory access costs. We present a CPU-based 3D interpolator, using SSE vector operations, that is faster than any previously published solution.

In this paper, a data parallel algorithm called GPURetinex is proposed to parallelize the Retinex algorithm on GPGPU. The computing of the Gaussian blur in the GPURetinex adopts separable convolution kernels to reduce the computation and the internal data transfer. The data distribution of parallel Gaussian blur convolution adopts a horizontal stripe method. Each thread reads pixels of a horizontal stripe of the image to implement the Gaussian blur convolution. The Gaussian blur utilizes texture memory and constant memory to improve efficiency. The data distribution in the log-domain subtraction and normalization steps uses a square subimage method. Each thread computes the two operations for all pixels within its square subimage. A parallel reduction method is devised to find the maximum and minimum values of the log-domain subtraction image. Threads within a grid communicate by global memory and shared memory. In our experiments, the GT200 GPU and CUDA 3.0 are deployed. The experimental results show that the GPURetinex can gain 23x speedup compared with CPU-based implementation on the images with 2048 x 2048 resolution. Our experimental results indicate that using CUDA can move the Retinex algorithm to the GPU hardware and achieve acceleration to gain the real-time performance.

Because transistor size has continued to fall while processor clock frequency has remained fairly static, the trend in computer architecture has been to develop multicore processors. To take full advantage of multicore processors, applications must be amenable to parallelization. Many imaging applications can benefit from multicore technology because they consist of localized operations. Hence, there are a multitude of multicore platforms and parallelization strategies that can be applied to imaging problems. A variety of multicore architectures have been introduced, including more traditional shared-memory parallel architectures and more exotic tiled multicore architectures. Tiled multicore architectures have many processor cores connected by an on-chip interconnection network. With these features, tiled multicore architectures can support a variety of parallel programming patterns. In this paper, we investigate the performance and scalability of a particular imaging application--Canny edge detection--on the Tilera Tile64 tiled multicore processor. We apply various parallel programming patterns, including divide and conquer and geometric decomposition, and draw conclusions about their suitability to the application and the target platform. As part of our study, we will develop implementations in which parallelism is explicitly managed in the program and implementations in which parallelism is managed by compiler directives and run-time systems.

Combining consumer electronics, digital entertainment, and the personal computer platform has become one of the key driving forces of modern PC development. In this paper, we presented the implementation of a UVD-accelerated decoder MFT through Microsoft DirectX Video Acceleration (DXVA) interface for enhancing the performance of drag-and-drop transcoding of high-definition videos running on Windows 7 platforms. In which the uncompressed video is downsampled by a GPU-based resize to conserve memory bandwidth between the GPU and CPU. Experimental results show this UVD-accelerated decoder MFT is able to perform real-time playback of high-definition video on a PC with extremely low CPU usage. Combining the GPU-based resolution scaler and the driver feedback, the proposed technology can double the speed of video transcoding of 1080p (1920x1080) video content on a processor with an integrated graphics unit by using less than half CPU capability compared to software VC1 and H.264 decoders. Although modern high-speed multi-core CPUs with advanced single-instruction multiple-data (SIMD) architecture may outperform the UVD unit in video decoding, UVD acceleration will always be helpful in off-loading the CPU's task and increasing the computational capacity of PC platforms.

2D image deconvolution is an important and well-studied problem with applications to image deblurring and restoration. Most of the best deconvolution algorithms use natural image statistics that act as priors to regularize the problem. Recently, Krishnan and Fergus provide a fast deconvolution algorithm that yield results comparable to the current state of the art. They use a hyper-Laplacian image prior to regularize the problem. The resulting optimization problem is solved using alternating minimization in conjunction with a half-quadratic penalty function. In this paper, we provide an efficient CUDA implementation of their algorithm on the GPU. Our implementation leverages many well-known CUDA optimization techniques, as well as several others that have a significant impact on this particular algorithm. We discuss each of these, as well as make a few observations regarding the CUFFT library. Our experiments were run on an nVidia GeForce GTX 260 GPU. For a single channel image of size 710 x 470, we obtain 40.6 fps, while on a larger image of size 1900 x 1266, we get 5.8 fps (without counting disk I/O). In addition to linear performance, we believe ours is the first implementation to perform deconvolutions at video rates.

This paper addresses the problem of stitching Giga Pixel images from airborne images acquired over multiple flight paths of Costa Rica in 2005. The set of input images contains about 10,158 images, each of size around 4072x4072 pixels, with very coarse georeferencing information (latitude and longitude of each image). Given the spatial coverage and resolution of the input images, the final stitched image is 294,847 by 269,195 pixels (79.3 Giga Pixels). Our approach is to utilize the coarse georeferencing information for initial image grouping followed by an intensity-based stitching of groups of images. This group-based stitching is highly parallelizable. The stitching process results in image patches that can be cropped to fit a tile of an image pyramid frequently used as a data structure for fast image access and retrieval. We report our preliminary experimental results obtained when stitching and pyramid tiling a 4 Giga Pixel image from the input images at one fourth of their original spatial resolution using a single core on our eight core server. As the processing requires parallel computing approaches in order to generate the full resolution image, we are collecting actual benchmarks on parallel hardware platforms.

This paper formalizes one of a major insight into a class of algorithms that relate between parallelism and performance. The purpose of this paper is to define a class of algorithms that trades off parallelism for quality of result (e.g. visual quality, compression rate), and we propose a similar method for algorithmic classification based on NP-Completeness techniques, applied toward parallel acceleration. We will define this class of algorithm as "GPU-Complete" and will postulate the necessary properties of the algorithms for admission into this class. We will also formally relate his algorithmic space and imaging algorithms space. While GPUs are merely one type of architecture for parallelization, we show that their introduction into the design space of printing systems demonstrate the trade-offs against competing multi-core, FPGA, and ASIC architectures. While each architecture has its own optimal application, we believe that the selection of architecture can be defined in terms of properties of GPU-Completeness. For a well-defined subset of algorithms, GPU-Completeness is intended to connect the parallelism, algorithms and efficient architectures into a unified framework to show that multiple layers of parallel implementation are guided by the same underlying trade-off.

With the ever-increasing printing resolution and speed, digital presses present high demands for the processing power of the Raster Imaging Process (RIP). Today's massively parallel GPUs can potentially provide a high-performance and cost-effective solution for RIPs. However, error diffusion, as a major stage in the printer imaging pipeline, is inherently serial in its original form. In this paper, we investigate the suitability of the GPU for a parallel implementation of the error diffusion algorithm. We demonstrate a high-performance GPU implementation achieved by efficiently managing the memory usage to meet the hardware constraints. Our GPU implementation achieves a 10-20x speedup over a sequential CPU error diffusion with comparable image quality. We conduct various experiments to study the performance and quality tradeoffs for differences in parallelism, randomization, block and image sizes.

With the release of an eight core Xeon processor by Intel and a twelve core Opteron processor by AMD in the spring of 2010, the increase of multiple cores per chip package continues. Multiple core processors are common place in most workstations sold today and are an attractive option for increasing imaging performance. Most imaging algorithms, especially large difference of Gaussian filters, segmentation, and region finding are very compute intensive. In this paper we present our work in optimizing the performance of different imaging algorithms to run on standard multi-core Windows workstations. Our work leverages the OpenMP libraries in C++ to create parallel for loops. We will present our experience in getting the best performance for imaging algorithms from these libraries.

Graphical Processing Units (GPU) architectures are massively used for resource-intensive computation. Initially dedicated to imaging, vision and graphics, these architectures serve nowadays a wide range of multi-purpose applications. The GPU structure, however, does not suit all applications. This can lead to performance shortage. Among several applications, the aim of this work is to analyze GPU structures for image analysis applications in multispectral to ultraspectral imaging. Algorithms used for the experiments are multispectral and hyperspectral imaging dedicated to art authentication. Such algorithms use a high number of spatial and spectral data, along with both a high number of memory accesses and a need for high storage capacity. Timing performances are compared with CPU architecture and a global analysis is made according to the algorithms and GPU architecture. This paper shows that GPU architectures are suitable to complex image analysis algorithm in multispectral.

We have investigated the computational scalability of image pyramid building needed for dissemination of very large image data. The sources of large images include high resolution microscopes and telescopes, remote sensing and airborne imaging, and high resolution scanners. The term 'large' is understood from a user perspective which means either larger than a display size or larger than a memory/disk to hold the image data. The application drivers for our work are digitization projects such as the Lincoln Papers project (each image scan is about 100-150MB or about 5000x8000 pixels with the total number to be around 200,000) and the UIUC library scanning project for historical maps from 17th and 18th century (smaller number but larger images). The goal of our work is understand computational scalability of the web-based dissemination using image pyramids for these large image scans, as well as the preservation aspects of the data. We report our computational scalability benchmarks using the Microsoft Seadragon library for building image pyramids, hyper-threading for computation execution and various hard drive configurations such as RAID drives for input/output operations. The benchmarks are obtained with a map (334.61 MB, JPEG format, 17591x15014 pixels). The discussion combines the speed and preservation objectives.

We present real-time 3D image processing of flash ladar data using our recently developed GPU parallel processor kernels. Our laboratory and airborne experiences with flash ladar focal planes have shown that per laser flash, typically only a small fraction of the pixels on the FPA actually produce a meaningful range signal. Therefore, to optimize overall data processing speed, this large quantity of uninformative data should be filtered out and removed from the data stream prior to the mathematically intensive data processing. This front-end pre-processing, which largely consists of control flow instructions, is specific to the exact type of flash ladar focal plane array used. The valid signals along with their corresponding inertial navigational metadata are then transferred to a GPU device to perform range-correction, geo-location, and ortho-rectification on each 3D data point so that data from multiple frames can be properly tiled together either to create a wide-area map or to reconstruct an object from multiple look angles. GPU parallel processor kernels were developed using the OpenCL application programming interface. Post-processing to perform fine registration between data frames via complex iterative steps also benefits greatly from this type of high-performance computing. The performance improvements obtained using GPU processing to create corrected 3D images and for frame-to-frame fine-registration are presented.

In this paper, we present a fast iterative MR image reconstruction algorithm taking advantage of the prevailing GPGPU programming paradigm. In clinical environment, MR image reconstruction is usually performed via fast Fourier transform (FFT). However, imaging artifacts (signal loss and signal distortions) resulting from susceptibility-induced magnetic field inhomogeneities degrade the quality of reconstructed images. These artifacts must be addressed using accurate modeling of the physics of the system coupled with iterative reconstruction. We have developed a reconstruction algorithm with improved image quality at the expense of computation time. Hence, an implementation on GPUs is proposed, achieving significant speedup. The proposed algorithm implements a conjugate gradient reconstruction using explicit Fourier transform (FT) in order to model the field inhomogeneity and its gradients. In addition, a smoothing constraint is included in the form of sparse matrix regularization in order to reduce noise in reconstructed images. We apply the compilation optimizations from levels of algorithm, program code structures, and specific architecture performance tuning, featuring both our MRI reconstruction algorithm and GPU hardware specifics. The current GPU implementation produces accurate image estimates while accelerating the reconstruction by two orders of magnitudes. Future directions include further optimization of current and higher-dimension approach.

The future multimodal user interfaces of battery-powered mobile devices are expected to require energy-efficient computationally costly image analysis techniques GPU computing is well suited for parallel processing. The addition of programmable stages and high precision arithmetic provide for opportunities to implement energy-efficient complete algorithms on GPU. At the moment the first mobile graphics accelerators with programmable pipelines are available, enabling the GPGPU implementation of several image processing algorithms. In this context, we consider a face tracking approach that uses efficient gray-scale invariant texture features and boosting. The solution is based on the Local Binary Pattern (LBP) features and makes use of the GPU on the pre-processing and feature extraction phase. We have implemented a series of image processing techniques in the shader language of OpenGL ES 2.0, compiled them for a mobile graphics processing unit and performed tests on a mobile application processor platform (OMAP3530). In our contribution, we describe the challenges of the design on a mobile platform, present the performance achieved and provide measurement results for the actual power consumption in comparison to using the CPU (ARMv7) on the same platform. Our experiments show how a considerable speedup of image processing applications can be achieved by the simultaneous use of the GPU and the CPU on mobile devices.

Traditional methods of multi-view stereo (MVS) via volumetric graph-cut formulate the multi-view scene reconstruction problem into a computationally tractable global optimization using graph-cut. The optimal surface can be obtained as the max-flow/min-cut solution of the weighted graph. With the resolution of cubical voxels become larger, the reconstruction accuracy is increased gradually, however, the photo consistency estimation for voxels and the graph-cut computation increasing rapidly, if more edges between neighbor voxel are added into graph, the desktop computer nearly can't handle the problem. Therefore, the contradiction between computation and accuracy needs to be reduced urgently. In our paper, we are focusing on improving the performance of graph-cut based MVS algorithm with the help of multi-core CPUs. We have developed a system to demonstrate the clustering and it can utilize the parallel optimization algorithm for this problem. A key technical contribution is the voxels clustering algorithm, it divides the voxels into several overlapping clusters, after that graph-cut algorithm can be used to reconstruct each area of the surface in parallel. Finally, the optimization result in each subgraph is collected together and the labels on overlapped voxels are forced to be consistent interactively. This technique demonstrated faster graph based multi-view volumetric reconstruction computations when multiple CPU cores are available. The reconstruction results are comparable with the state-of-art MVS methods.

As commercial printing presses become faster, cheaper and more efficient, so too must the Raster Image Processors (RIP) that process and feed them data to print. Digital press RIPs, however, have been challenged to both meet the ever increasing print performance of the latest digital presses, and the more common use of advanced pixel processing such as ICC color profile specified color spaces and transparent image layers. As a result, the cost of the RIPs deployed at some of the more demanding Print Service Providers (PSP) can exceed $250,000. This paper explores the challenges encountered when implementing a GPU accelerated driver for the open source Ghostscript Adobe PostScript and PDF language interpreter targeted at accelerating PDF transparency for high speed, large page size commercial presses. It further describes our solution, including an image memory manager for tiling input and output images, a cache of dynamically compiled GPU programs for an accelerated ICC v4 compatible color transformation engine, and an Adobe PDF compatible multiple image layer blending engine. The result, we believe, is the foundation for a scalable, efficient, distributed RIP system that can meet current and future RIP requirements for a wide range of commercial digital presses.

The tracking of infrared small targets has been a key technology in the field of satellite early warning, precise guidance, surveillance and detection. The paper presents a low cost FPGA based solution for a real-time infrared small target tracking system. A specialized architecture is presented based on a soft RISC processor capable of running kernel based mean shift tracking algorithm. Mean shift tracking algorithm is realized in Nios II soft-core With SOPC technology. Though mean shift algorithm is widely used for target tracking, the original mean shift algorithm can not be directed used for infrared small target tracking. As infrared small target only has intensity information. So an improved mean shift algorithm is presented in this paper. How to describe target will determent whether target can be tracked by mean shift algorithm. Because color target can be tracked well by mean shift algorithm, imitating color image expression, spatial component and temporal component are advanced to describe target, which forms pseudo-color image. The experimental results show that infrared small target is tracked stably in complicated background. In order to improve the processing speed parallel technology and pipeline technology is taken. Two RAM are taken to stored images separately by ping-pong technology. A FLASH is used to store mass temp data.

Nowadays, there are increasing research interests in Free viewpoint Television (FTV) that offers arbitrary views of 3D scene. View synthesis is important for prediction-based compression and novel view display in FTV and other multiview imaging application such as 3DTV. View synthesis consists in rendering images of a scene as if they were taken from a virtual viewpoint different from all the viewpoints of the real views. This paper proposes a novel approach for multiview synthesis in which the process of view synthesis is based on the relative affine structure. The advantage is that photographs of real scenes can be used as a basis to create very realistic images, and rendering time is decoupled from the complexity of the scene. The virtual camera position is specified in an uncalibrated setting-up via the interpolation of the motion information among the reference views. This method yields a parametric family of camera poses that describes a smooth trajectory in the Euclidean space as the parameters vary continuously. The new synthesized images can be rendered from virtual cameras moving on the given parameterized trajectories. Synthetic and real experimental results illustrate that the method has advtanges of low computational complexity without the error produced from depth estimation.