EUV Lithography (SPIE Press Book)

Table of Contents

1.1 Introduction

1.2 The Early Stage of Development—1981 to 1992

1.3 The Second Stage of Development—1993 to 1996

1.3.1 Two-Mirror Imaging System Development

1.3.2 Three-Mirror Imaging System Development

1.3.3 MOS Device Demonstration Using EUVL

1.4 Other Developments in Japan and Europe

1.5 The Development of Individual Technologies

1.5.1 Selection of the Exposure Wavelength

1.5.2 Design of Reflective Imaging Systems

1.5.3 Fabrication and Evaluation of Aspherical Mirrors

1.5.4 Multilayer Coatings and Reflection Masks

1.5.5 EUV Resist Development

1.5.6 EUV Light Source Development

1.6 EUVL Conferences

1.7 Summary

1.8 Acknowledgements

1.9 References

2.1 Introduction

2.1.1 Background

2.1.2 Need for a Revolutionary Approach

2.2 Formation of the LLC

2.2.1 Vision

2.2.2 Implementation

2.2.3 Organizational Structure

2.3 Program Structure 2

2.3.1 Organization

2.3.2 Risk Management

2.3.3 Reporting

2.3.4 Documentation

2.4 Program Results

2.4.1 Technical accomplishments

2.4.2 IP Portfolio

2.4.3 Program Statistics

2.4.4 Delays

2.5 Retrospective observations

2.5.1 Improvements

2.5.2 External Issues

2.5.3 Benefits

2.6 Status of EUV Development at the end of LLC 2

2.6.1 Risk Reduction

2.6.2 Industry involvement

2.7 Summary

2.8 Acknowledgements

2.9 Appendix A - Major Accomplishments

2.10 Appendix B - Patents

2.11 References

3.1 Introduction

3.2 EUV Source Requirements

3.2.1 Definition of EUV Source

3.2.2 Joint Specifications

3.2.3 Throughput Model

3.3 DPP and LPP Source Technologies

3.3.1 Discharge-Produced Plasma (DPP)

3.3.2 Laser-Produced Plasma (LPP)

3.4 EUV Source Performance

3.4.1 Conversion Efficiency of EUV Sources

3.4.2 EUV Source Performance Results

3.4.3 Source Components and Their Lifetimes

3.5 Summary and Future Outlook

References

4A.1 Introduction

4A.2 Properties of EUVL Systems

4B.1 General EUVL Optical Design Considerations

4B.2 EUV Microsteppers

4B.2.1 "10X" Microstepper

4B.2.2 Microexposure Tool (MET)

4B.3 Engineering Test Stand (ETS)

4B.4 Six-Mirror EUVL Projection Systems

4B.4.1 Feasibility

4B.4.2 Concepts with Concave/Primary Mirrors

4B.4.2 Concepts with Convex Primary Mirrors

Acknowledgements

References

4C.1 Introduction

4C.2 Specification

4C.3 Projection Optics

4C.4 Effect of Substrate Errors on Imaging Performance

4C.5 Low-Frequency (Figure) Errors

4C.7 High-Spatial-Frequency Errors

4C.8 Influence of Coatings on Roughness Specification

4C.9 Calculation of Surface Errors

4C.10 Uniformity

4C.11 Substrate Materials

4C.12 Fabrication

4C.13 Metrology

4C.14 Mounting and Assembly

4C.15 Alignment

4C.16 Condenser Optics

Acknowledgements

References

4D.1 Overview and History of EUV Multilayer Coatings

4D.2 Choice of ML Materials and Wavelength Considerations

4D.3 Multilayer Deposition Technologies

4D.4 Theoretical Design

4D.5 High Reflectivity, Low Stress, and Thermal Stability Considerations

4D.6 Optical Constants

4D.7 Multilayer Thickness Specifications for Imaging and Condenser EUVL Mirrors

Acknowledgements

References

5.1 Introduction

5.2 Target Accuracy

5.3 Techniques for Angstrom-scale EUV Wavefront Measurement Accuracy

5.3.1 Spherical-Wave Illumination

5.3.2 Basic Testing Requirements

5.3.3 Knife-Edge Test

5.3.4 Point-Diffraction Interferometer

5.3.5 Phase-Shifting Point-Diffraction Interferometer

5.3.6 Shearing Interferometery

5.3.7 Hartmann Wavefront Sensor

5.3.8 EUV Interferometry Examples

5.3.9 Aerial Image Monitors

5.3.10 Calibration Techniques

5.4 Intercomparison

5.4.1 Visible-Light and EUV Interferometry

5.5 Future Directions

5.5.1 At-Wavelength Optical Testing in Commercial Lithography Applications

5.5.2 EUV Optical Testing in Other Areas

References

6A.1 Introduction

6A.1.2 Survey of Recent Lifetime Results

6A.2 Fundamentals of Optics Contamination

6A.2.1 Causes of Projection Optics Contamination

6A.2.2 Theoretical Models of Optics Contamination

6A.3 Optics Contamination Control

6A.3.1 Measurements of Optics Lifetime

6A.3.2 Measurement of Optics Contamination (In-Situ Metrology)

6A.3.3 Environmental Control Strategy

6A.3.4 Development of Contamination-Resistant Capping Layers

6A.3.5 Cleaning of Optics Contamination

6A.3.6 Novel Approaches to Contamination Control

6A.4 Summary and Future Outlook

References

6B.1 Introduction

6B.1.1 EUV Lithography Challenges

6B.1.2 EUV Sources

6B.1.3 EUV Collector Optics

6B.2 Collector Lifetime Status and Challenges

6B.2.1 Mechanism of Reflectivity Degradation

6B.2.2 Erosion and Deposition: A Binary Collision Approximation Study of Sn Interaction with Ru Surfaces

6B.2.3 Sn Chemical Removal

6B.3 Summary

Acknowledgements

References

6C.1 Introduction

6C.2 Overview of Normal-Incidence Collector Mirrors

6C.3 Collector Performance

6C.3.1 Erosion by Fast Ions and Lifetime Calculation

6C.3.2 Contamination and Optics Cleaning

6C.3.3 Thermal Load and Layer Intermixing

6C.4 Summary

Acknowledgements

References

7.1 Introduction

7.2 EUV Mask Structure and Process Flow

7.3 Mask Substrate

7.3.1 Mechanical Property Requirements

7.3.2 Surface Figure Requirement

7.3.3 Defect Requirements

7.4 Mask Blank Fabrication

7.4.1 Multilayer Deposition Process

7.4.2 Multilayer Characterization

7.4.3 Multilayer Performance Improvement Techniques and Defect Mitigation

7.4.4 Multilayer Defect Inspection

7.4.5 Multilayer Defect Repair

7.4.6 Multilayer Defect Compensation

7.5 Absorber Stack and Backside Conductive Coating

7.5.1 Absorber Layer

7.5.2 Buffer Layer

7.5.3 Antireflection Coating

7.5.4 Shadowing Effect

7.5.5 Bossung Curve Assymetry and Focus Shift

7.5.6 Backside Conductive Coating and Mask Handling

7.6 Mask Patterning

7.6.1 E-Beam Writing

7.6.2 Absorber Stack Etch

7.6.3 Absorber Defect Inspection

7.6.4 Absorber Defect Repair

7.6.5 Buffer Layer Etch

7.6.6 Buffer Layer Defect Inspection and Repair

7.7 Mask Cleaning

7.8 Advanced Mask Structure

7.8.1 Etched Binary Mask

7.8.2 Attenuated Phase Shift Mask

7.8.3 Alternating Phase Shift Mask

7.8.4 Modified Alternating Phase Shift Mask

7.9 Summary and Future Outlook

Acknowledgements

References

8.1 Introduction

8.2 Earliest EUV Resist Imaging

8.3 Absorption Coefficients of EUV Photoresists

8.3.1 Absorption Coefficient Definitions

8.3.2 Absorption Cross-Sections of the Elements

8.3.3 Methods for Determining EUV Absorbance

8.4 Multilayer Resists and Pattern Transfer

8.4.1 Multilayer Resist Approaches

8.4.2 Defects in Ultrathin Resist Films

8.4.3 Pattern Transfer of UTR into Hard Masks

8.4.4 Integration of UTRs into Integrated Circuit Manufacturing Processes

8.5 Resist Types

8.5.1 Environmentally Stable Chemically Amplified Photoresists (ESCAP)

8.5.2 KRS Photoresists

8.5.3 PMMA

8.5.4 Negative Resists

8.5.5 Resists with Silicon or Boron

8.6 PAGs and Acids

8.6.1 Acid Diffusion

8.6.2 New PAGs for EUV

8.6.3 Exposure Mechanisms

8.7 Line Edge Roughness

8.7.1 Added Base

8.7.2 Polymer Size

8.7.3 Shot Noise

8.7.4 Film Quantum Yield

8.8 Summary and Future Outlook

Acknowledgements

Notes and References

9.1 Introduction

9.2 EUV Tool Design Considerations

9.3 EUV Microstepper

9.3.1 MS-13 Tool Concept

9.3.2 EUV Source

9.3.3 EUV Optics

9.3.4 Tool Subsystems

9.3.5 Tool Subsystems testing

9.4 Reticle Imaging Microscope

9.4.1 RIM-13 Tool Architecture

9.4.2 EUV Source

9.4.3 EUV Illumination

9.4.4 Reticle Imaging

9.4.5 EUV Microscope

9.4.6 Visible Microscope

9.4.7 Tool Subsystems

9.4.8 EUV Reticle Aerial Image Capture Results

9.4.9 Software

9.5 Summary and Future Outlook

Acknowledgments

References

10.1 Introduction

10.2 Illumination Optics

10.2.1 Illumination Optics Design

10.2.2 Source Requirements

10.2.3 Thermal Loading of Illuminator

10.3 Projection Optics

10.3.1 Numerical Aperture

10.3.2 Magnification and Field Size

10.4 Stages

10.4.1 Reticle Stage and Wafer Stage

10.4.2 Reticle Chuck

10.4.3 Wafer Chuck

10.5 Sensors

10.5.1 Reticle Focus Sensor

10.5.2 Wafer Focus Sensor

10.5.3 Wafer Alignment Sensor

10.5.4 Aerial Image Sensor

10.5.5 Dose Sensor

10.6 Handling Systems

10.6.1 Reticle Handling System

10.6.2 Wafer Handling System

10.7 Vacuum and Environment System

10.8 Budgets

10.8.1 Overlay Budget

10.8.2 Focus Budget

10.8.3 Wafer Throughput Budget

10.9 Summary

Acknowledgements

References

11.1 Introduction: The Benefits of EUV Imaging

11.2 Imaging with the 0.1-NA ETS Optic

11.2.1 Static Imaging Characterization of the 0.1-NA ETS Optic

11.2.2 Low-k1 Printing With Modified Illumination

11.2.3 Determining the Impact of Limited Resist Resolution

11.2.4 Early Demonstration of Chromeless Phase-Shift-Mask Printing in the EUV Range

11.2.5 Buried Programmed Defect Printability Study

11.3 Imaging with the 0.3-NA MET Optic

11.3.1 Predicted Performance

11.3.2 Demonstrating Resist-Limited Performance

11.4 System Contributors to Line-Edge Roughness

11.4.1 LER Transfer from the Mask to the Wafer

11.4.2 Mask Roughness Effects on LER

11.4.3 Mask Roughness Effects on Printed Contact Size Variations

11.5 Flare in EUVL Systems

11.5.1 Sources of Flare and Estimating Flare from Surface Roughness

11.5.2 Flare Characterization of the Intel MET

11.5.3 Impact of Flare on Patterning Performance and Flare Variation Compensation

11.6 Summary

Acknowledgments

References

12.1 CoO Overview

12.1.1 SEMATECH Lithography CoO Historical Activities

12.1.2 General CoO Equations and Input Relationships

12.1.3 Lithography Global CoO Input Assumptions

12.1.4 Lithography Specific Product Parameters

12.2 Lithography Historical Cost and Price Trends

12.2.1 Historical Completed Wafer, Die, and Function Costs to Manufacture

12.2.2 Historical Photolithography Exposure Tool Price Trends

12.2.3 Historical Reticle Costs and Mask Usage Trends

12.3 Major Lithography CoO Parameter and Productivity Drivers

12.3.1 Example of 100nm Litho Patterning Metal 1 Level CoO within a 90nm Half Pitch Logic Device Manufacturing

12.3.2 Exposure Tool Cell Throughput (TPT)

12.3.3 Exposure Level Product Requirements (Yield, Send Aheads, and Rework)

12.3.4 DUV Source Consumables and Running Costs

12.3.5 Photoresist Cost Drivers and Photoresist Process Complexity

12.3.6 Reticle Cost Drivers

12.3.7 Litho Cell Equipment Reliability, Availability, and Maintainability (RAM)

12.4 General Observations on Litho Cell and CoO Improvements (past decade)

12.4.1 Exposure Tool Supplier CoO Improvement Factors

12.4.2 Optical Laser Source Improvements

12.4.3 Photoresist and Photoresist Processing

12.4.4 Reticle Improvements

12.4.5 FAB Automation Processing and Yield Controls

12.5 Brief CoO Considerations for Near Future Lithography Technologies

12.5.1 193nm Immersion Lithography (193i)

12.5.2 Extreme Ultraviolet Lithography (EUVL)

12.5.3 Maskless Lithography (ML2)

12.5.4 Nano Imprint Lithography (NIL)

12.6 Summary

12.7 Example Case Studies of Litho CoO Calculations

12.7.1 Example Case 1: Improved Yield at Expense of System Cost and/or TPT Performance

12.7.2 Example Case 2: Slight Improved Laser Source Power at Expense of Specialty Gas Costs

12.7.3 Example Case 3: Product Lots Reroute To Different Tool vs. Lot Hold

Acknowledgments

References