22nm-node logic lithography at the boundary of the resolution limit

The resolution of an optical-imaging system is governed by Rayleigh's law, P/2=k₁×λ/NA, where P is the minimum printable pitch, λ is the wavelength of the illuminating light, NA is the system's numerical aperture, and k₁ indicates the difficulty of the lithographic process. Historically, the semiconductor industry has been scaling down the minimum printable pitch for cost reduction and higher chip density by reducing λ/NA. State-of-the-art technology uses water immersion—NA_max = 1.35, n_wafer (wafer refractive index) = 1.44—with λ = 193nm. To be able to continue scaling, extreme-UV (EUV) (λ = 13.5nm) or water-immersion double patterning at λ = 193nm have been considered for next-generation technology, while λ = 157nm and high-index immersion (n>1.44) options were deselected because of technical stumbling blocks and low extendibility. For 22nm-node (a reference to the smallest feature size) logic technology, however, EUV is not available for high-volume manufacturing. Moreover, double patterning produces additional complexity and cost. Consequently, extension of water-immersion single patterning at λ = 193nm is being actively tested to bring resolution at or close to the printable limit. To enable single patterning, the shrinkage paradigm is being shifted in the direction of aggressively reducing k₁, which in turn complicates control of the image and severely restricts processing and design.

Here, we report our progress on a 22nm-node logic lithography technology in the context of a research alliance of IBM, GlobalFoundries, Toshiba, Renesas, and STMicroelectronics, focusing on single patterning of an active layer of a 0.1μm² six-transistor static random-access-memory (SRAM) cell of a planar device. At the date of this writing, the device is the smallest SRAM cell yet reported.^1,2

When the minimum k₁ approaches its practical limit (k₁~ 0.28), the manufacturable process window (i.e., the tolerable range of parameter variability) is often suboptimal because of fading image resolution. Consequently, successful patterning depends on integrating resolution-enhancement technology (RET) into the lithographic process, as well as design-for-manufacturability (DFM) techniques. In general, lithographic cell-area scaling is determined by the gate pitch and the contact pitch perpendicular to it. As the technology approaches the 22nm node, contacts become a limiter of cell size because of their faster decay in image quality relative to the pitch of lines and spaces. For the active layer of planar transistor devices, one newly identified challenge is printing 2D corner rounding at the jogs (i.e., steps in the y direction: see Figure 1). Because the gate pitch shrinks from 32nm-node technology onward without a corresponding advance in NA, both control of corner rounding and aggressive k₁ become critical factors in selecting RET options.

We used NA = 1.2 with strong off-axis illumination in both the x and y directions and redefined the design during lithographic optimization. Off-axis illumination of a mask uses oblique rather than vertical incident light for printing smaller pitches. This concurrent RET-design-optimization approach was intended to provide better printability for the minimum pitch as well as the jog of the active layer. In choosing the RET, we verified its usefulness by observing across-the-chip printability, which is limited by the process windows of critical features encompassing an anchor (tightest) pitch of 100nm, corner rounding at the jogs, and minimum isolated trench (spacing between the active regions). We decided critical features based on design priorities and the level of difficulty in lithographic printing. Recently, illumination-source- and mask-optimization techniques produced a better process window across the chip.^3–5 One key issue identified in illumination-source optimization is variation in weighting among the critical features,⁶ which can dramatically alter source shape and intensity distribution.

Figure 1. Top-down scanning-electron-microscope images of sequential process optimizations. (a) As-is print image, pre-optimization. (b) Development-time adjustment (15s). (c) Polarization tuning from x, y to x polarization. (d) Post-etch into target film.

Layer-specific lithographic process development is another key factor for the success of 22nm-node technology, since the process setup, including materials selection, relies on the balanced printing capability of the critical features across the layer. We have observed that thinning the resist improves the process window to a noticeable degree, and using an immersion top coat and a double antireflection-film coating is required in a hypernumerical-aperture (i.e., NA = 1.2) environment.⁷

Figure 1 presents a series of optimization processes showing that the high line-edge roughness component can be improved by minimal tuning of, for example, development-time adjustment and polarized illumination. Figure 2 shows an overlap image of the printed resist and a simulated printed image. The close agreement between the two provides a measure of the efficacy of the optical proximity-correction model and process development.

Figure 2. Overlap between the printed resist pattern and optical proximity correction (simulated printed image).

In summary, we were able to print an active layer of a 0.1μm² six-transistor SRAM cell for 22nm-node logic technology using single-patterning immersion lithography. The technique is aided by the use of strong off-axis illumination as well as by DFM and layer-specific lithographic process control. The goal of the present study was to define a lithography framework for 22nm-node technology. We will continue to fine-tune the approach towards cost-effective manufacturability and high yield.

This work was performed by the Research Alliance teams at various IBM research and development facilities.