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Journals Author Information Landing Page

To submit a manscript for consideration in a Special Section, please prepare the manuscript according to the journal guidelines and use the Online Submission System.


FORTHCOMING SPECIAL SECTIONS:

Extreme-Ultraviolet Lithography

Computational Lithography

Theory and Practice of MEMS/NEMS/MOEMS, RF MEMS, and BioMEMS

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS

Extreme-Ultraviolet Interference Lithography

Double-Patterning Lithography


October–December 2009

Extreme-Ultraviolet Lithography

Guest Editors:

Kevin Cummings

ASML
25 Corporate Circle
Albany, New York 12203
E-mail:kevin.cummings@asml.com

Kazuaki Suzuki
Nikon Corporation
201-9, Miizugahara, Kumagaya
Saitama, 360-8559, Japan
E-mail:kzsuzuki@nikongw.nikon.co.jp

Call for Papers: Lithography continues to drive progress in the integrated-circuit (IC) industry by allowing continued increases in density of devices while reducing the costs on a per transistor basis. However, the continued lithographic shrink that comes from the increasing numerical aperture of current-day ArF immersion scanners has reached its end and attempts to continue the shrink with these systems involves rapidly increasing complexity in the lithography and associated costs. Extreme-ultraviolet lithography (EUVL) is poised to become the next cost-effective IC manufacturing solution for multiple generations of lithographic shrinks. With the first generation of full-field EUVL scanners now available, critical elements of the technology are being evaluated at a level not previously possible. We are soliciting papers for this special section of JM3 that explore new developments, issues, and solutions for EUVL, including:

  • current activities and understanding gained with existing EUVL tools;
  • planned activities to understand and produce manufacturing capable tools;
  • integration of EUVL into semiconductor fabrication processes;
  • EUV sources, collectors, and illuminators;
  • EUV reticles, blank materials, defectivity, repair, and EUV reticle handling;
  • EUV resists, resolution, sensitivity, line edge roughness, and outgassing;
  • EUV optics, multilayer mirrors, and flare;
  • contamination and cleaning;
  • advanced imaging, optical proximity correction, reticle shadowing effect, and phase shift masks.

Manuscripts due March 6, 2009

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July-September 2009

Computational Lithography

Guest Editors:

Chris A. Mack
Lithoguru.com
1605 Watchhill Road
Austin, Texas 78703
Tel: 512-322-0980
E-mail: chris@lithoguru.com

Donis Flagello
ASML
8555 South River Parkway
Tempe, Arizona 85284
Tel: 480-383-4329
E-mail: donis.flagello@asml.com

Call for Papers: Computational lithography is a new phrase to describe the widening application of modeling to lithography for semiconductor manufacturing. Lithography simulation has been used as a research tool (performing experiments that would be difficult or impossible to do any other way), as a development tool (quickly evaluating options, optimizing processes, or reducing the number of experiments required), as a manufacturing tool (for determining process and tool settings and optical proximity corrections per design), and as a learning tool (to help provide a fundamental understanding of all aspects of the lithography process). While each of these applications are expanding today, the push toward lower k1and more complex resolution enhancement techniques in manufacturing has drastically increased the required amount of optical proximity correction and the need for more accurate modeling. Recently, computational lithography can be found from the back-end of the fab to the front-end of design, and is often the engine required to make design for manufacturing a reality. Papers are being solicited in the following areas:
  • First-principles models (optics and resist);
  • Fast, approximate (compact) models (optics and resist);
  • Algorithm speed and numerical accuracy;
  • Inverse image modeling in lithography;
  • Optimization of illumination shapes, mask design, and lens pupils;
  • Full-chip simulation methods;
  • Model calibration and portability;
  • Lithography tool, material, and process measurements needed for simulation;
  • Applications of computational lithography.

Closed for submissions.

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April-June 2009 and July-September 2009

Theory and Practice of MEMS/NEMS/MOEMS, RF MEMS, and BioMEMS

Guest Editor:

Yu-Cheng Lin
National Cheng Kung University
Department of Engineering Science
1 University Road, Tainan, Taiwan
E-mail: apcot08@conf.ncku.edu.tw

Call for Papers: The theory, design, fabrication, and characterization of MEMS/NEMS, BioMEMS, RF MEMS, and MOEMS have been making tremendous progress. Just one conference, APCOT2008, contains more than 500 presentations on these topics. We are calling prospective authors to submit worthwhile contributions in these fields for peer-reviewed and archived publication in a special section of JM3, regardless of whether they were presented at APCOT. The special section will be comprised of the following four subtopical areas (please pick one when submitting your manuscript):

  1. BioMEMS,
  2. Theory, Design, Fabrication, and Characterization of MEMS/NEMS,
  3. Physical and Chemical Sensors,
  4. or MOEMS and RF MEMS.

A cover letter indicating that the submission is intended for this special section should be included. If your paper was presented at APCOT2008, please note this in the cover letter and make a reference to it in the manuscript.

Closed for submissions.

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July–September 2009

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS

Guest Editors:

Rajeshuni Ramesham

Jet Propulsion Laboratory
California Institute of Technology
4800 Oak Grove Drive
Pasadena, California 91109
Tel: 818-354-7190
E-mail: Rajeshuni.Ramesham@jpl.nasa.gov

Allyson Hartzell
Boston Micromachines Corporation
30 Spinelli Place
Cambridge, Massachusetts 02138
E-mail: alh@bostonmicromachines.com

Call for Papers: The purpose of this special section is to provide a technical stage to publish recent advances made in reliability, packaging, testing, and characterization of microelectromechanical systems (MEMS) and micro-optoelectromechanical systems (MOEMS) for various applications. We are soliciting high-quality papers on the following topics:

(1) packaging process reliability, including packaging materials, assembly processes, bonding materials, wafer-level packaging, high-vacuum packaging, hermeticity, leak testing, new testing tools to monitor hermeticity, thin-film getters and activation techniques, packaging without hermeticity, MEMS assembly cleanroom science, issues in integration of MEMS/MOEMS and ICs/ASICs/FPGAs, nondestructive evaluation of packaged systems (x-ray, acoustic microscopy, IR), effects of extreme and harsh environments (low and high temperature, radiation, shock, vibration), commercial-off-the-shelf (COTS) solutions, simulations/models, lead-free solder, and predictions of life of packaged MEMS systems;

(2) BEOL process reliability issues, including production and yield improvement, yield improvement by reducing stiction, parametric test methods and/or test structures used to assure fabrication processes, release methods and techniques, yield modeling and process control methodologies;

(3) reliability methodology, including aging, dormancy, early life failures, accelerated life testing, predictive models, acceleration factors, design of experiments, physics of failure, reliability in design, measurement techniques and properties, data reduction and visualization, scaling issues, reliability tool development, automation, and device/system reliability;

(4) reliability of surfaces, including stiction, adhesion, lubrication, critical point drying methods, self-assembled monolayers (SAMs) or other coating materials, tribology, surface molecular contamination, particulate contamination, and contact resistance;

(5) reliability of materials, including fracture, static and cyclic fatigue, wear, and life-cycle predictability;

(6) testing methods, including qualification of devices or systems, environmental testing (shock, vibration, temperature extremes, humidity, power cycling, contact cycling), highly accelerated lifetime testing (HALT), verification, and automation;

(7) standards development, including testing and measurement standards of devices or MEMS materials properties;

(8) characterization methods, including metrology tool development, laser Doppler vibrometry, interferometric methods, confocal microscopy, automation, calibration, and comparison to models; and

(9) failure analysis, including identification of failure modes and mechanisms, novel analysis techniques, novel tools, and case histories.

The scope of this special section includes all new and interesting aspects of reliability, packaging, testing, and characterization of MEMS and MOEMS. Articles based on theoretical, experimental, and simulation results will be considered for publication. Manuscripts should be submitted to SPIE according to the journal guidelines. A cover letter indicating that the submission is intended for this special section should be included. All papers for this special section, both solicited and unsolicited, will go through the standard journal review process.

Closed for submissions.

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April–June 2009

Extreme-Ultraviolet Interference Lithography

Guest Editor:

Franco Cerrina
University of Wisconsin–Madison
Department of Electrical and Computer Engineering
Madison, Wisconsin 53706
Tel: 608-265-3916
Fax: 608-265-3811
E-mail: fcerrina@wisc.edu

Call for Papers: The development of extreme ultraviolet lithography (EUVL) continues at an accelerated pace. Today, industry is looking at EUVL for the 22-nm node, and below. Optics, sources, masks, and resist materials are all objects of intense research. Photoresists are a gating component of EUVL, because of the conflicting requirements of sensitivity, resolution, and line edge roughness. Differences in the energy absorption and photoacid generator excitation yield a behavior of resist materials in the EUV that is different from the deep ultraviolet region. Thus, it is critical that we explore the synthesis, formulation, and performance of new materials for EUVL. This development of advanced imaging materials is hampered by the scarcity of EUVL exposure systems, and by the limited access to these tools. There is a need for alternative exposure systems, where novel materials can be tested and characterized quickly, economically, and without fear of contamination for the optics. Interferometric lithography (IL) is such a technique—in its simplest form, two coherent beams interfere to form a high-density fringe pattern that exposes the resist material. The uniformity, large area, and simplicity of operation make this fringe pattern ideal for the study of resist materials; several systems have been built for ArF lithography, including immersion. The extension of IL to the EUV region is a natural progression, and has made high-resolution, simple, and fast exposure systems available to the general research community. These exposure tools, based on the use of diffractive optics in various mounts, have shown patterning ability to the 10-nm region. There have been several proposals for interferometric setups to be installed on synchrotrons or in laboratories using various types of EUV sources. Systems using two, three, and four beams have been demonstrated. Holographic lithography in the EUV has been proposed and demonstrated. At the current stage of EUVL development, it is important to review existing capabilities and proposed approaches. Thus, papers are being solicited for the following areas: EUV interferometry lithography (EUV-IL), exposure systems, masks, novel concepts, sources for EUV-IL, theory, applications, and novel ideas.

Closed for submissions.

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January–March 2009

Double-Patterning Lithography

Guest Editor:

William H. Arnold
ASML
8555 South River Parkway
Tempe, Arizona 85284
Tel: 480-383-4034
Fax: 480-383-4518
E-mail: bill.arnold@asml.com

Shrinking feature sizes through high-resolution optical lithography continues to drive progress in the semiconductor industry by increasing device density while simultaneously reducing fabrication costs per transistor. Continuing the lithographic shrink is the highest priority of many workers in this field. Recently, with the introduction of 1.35-NA ArF immersion scanners, the smooth progress due to numerical aperture increase has come to an end. Water-immersion single-exposure lithography is limited to about 40 nm half-pitch with a NA of 1.35. Extension of immersion with high-index fluids and glasses is theoretically possible, but faces severe challenges in technology, economics, and timing. In order to extend water immersion lithography further, much attention is given to reducing effective k1 to less than 0.25 using double-patterning lithography (DPL). DPL can take many potential forms, including pitch division through successive lithography and etch patterning steps, frequency doubling using spacer or self-aligned processes, as well as innovative processes requiring nonlinear resist exposure. Fundamentals such as process capability, yields, cycle time, and overall cost will determine which forms will be used for device manufacturing. This special section of JM3 will include papers that explore the unique challenges of double patterning for device manufacturing. Papers are being solicited in the following areas:

  • novel wafer processes for double patterning;
  • applications of DPL to semiconductor device fabrication;
  • resist materials for double exposure and double patterning;
  • reticle technology for DPL;
  • error budgets for tools, reticles, and metrology in support of double patterning;
  • scanner tool optimization for double patterning; metrology requirements and solutions for DPL;
  • OPC and RET techniques related to DPL;
  • split algorithms for DPL layout; and cost of ownership for DPL.

Closed for submissions.

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