Tuesday, 27 February 2007
Double patterning technology emerges as preferred solution for production at the 32nm node
SPIE Fellow Dr. Burn Lin, Taiwan Semiconductor Manufacturing Co., Ltd., presents an invited paper to a packed ballroom at SPIE Advanced Lithography 2007 about the promise of 2-photon lithography. 2-photon makes possible the rapid prototyping and production of three dimensional chip features.
The buzz around the presentations in the Double Patterning Technology Session, chaired by Han-Ku Cho, SAMSUNG Electronics Co., Ltd. (South Korea) and Bruce W. Smith, Rochester Institute of Technology, is emblematic of how dramatically dual patterning lithography is emerging as the manufacturing method of choice at the 32 nm node and beyond. Mircea Dusa, ASML, presented interesting research on how the memory demands of mobile devices is driving the need for lithographic patterning capability that is beyond resolution of ArF water-based immersion tools. In parallel, Smith went on to say, EUV and high-index fluid-based immersion ArF lithography are still under development and is questionable whether they will be ready to timely meet resolution needs from most aggressive memory designs. As a consequence, dual patterning to double the pitch appears to be an option calling for more and more consideration.
The emergence of dual pattern lithography is certainly reflected at the SPIE Advanced Lithography 2007 Exhibition, which opened this morning to large crowds of attendees eager to discuss new developments with tool vendors. Nikon, for example, has announced the shipment of a 45 nm capable immersion lithography system to a major IC manufacturer. The system is targeted for mass production of 45 nm devices and can also be used for development of 32 nm devices and double patterning.
Around 20 women from a variety of companies involved in lithography attended the Women in Optics (WiO) Lunch on Tuesday. At the event, Advanced Lithography Symposium Chair Roxann L. Engelstad, University of Wisconsin/Madison, spoke about the WiO Technical Community, and ways for women to become more involved in SPIE activities, such as volunteering to serve on program committees. Attendees also used the time to network and share information about their research.
Monday, 26 February 2007
Industry leaders lay out roadmap for 32-nm lithography
Delegates settle in to listen to leaders in the sphere of semiconductor lithography talk about where the industry is headed at the SPIE Advanced Lithography Plenary Session.
SPIE Advanced Lithography 2007, the biggest meeting in the semiconductor industry, got underway in earnest this morning with the beginning of the Plenary Sessions, which took place before standing room crowds. Dr. Hans Stork of Texas Instruments kicked off the plenaries with his talk, "Nanoscale Patterning Challenges for CMOS Density Scaling,"
He began by suggesting that the most compelling use of mobile technology in the near future is the enhancement of the human interface through video. Since their introduction in the early 1980s, he explained, cell phones - the most likely candidate for mobile video - have increased in complexity and decreased in size due to successful integration of technologies. Successful integration has kept up with consumer demand for more functionality at a lower cost. However, he predicted, the next billion users of mobile technology will likely come from emerging markets such as China and India. This poses some difficult engineering challenges that arise from these new consumers' expectations. Namely, that manufacturers will be able to produce twice as many die on a wafer in a generation, achieve a better than 50% logic area shrink, attain more than a 20% performance improvement, use same or lower power, and do this all at a reasonable cost.
However, Dr. Stork cautioned, there are many difficulties to overcome. There is the voltage barrier around 1V, velocity limitations with logic density scaling, and variability from lot-to-lot. Also, contrary to the paradigm of each device working alike, there are local, unpredictable variations between neighboring devices as well as global process variations, and although immersion lithography has shown steady progress, at the 32-nm node we find that device scaling outpaces NA scaling, new defectivities emerge, and a NA ceiling of 1.35 is reached.
Dr. Stork addressed these issues and discussed the inherent tradeoffs between density and performance scaling for CMOS products.
Mr. George Gomba of IBM then gave a talk about how IBM's collaborative environment and partnerships have advanced the company's immersion lithography strategy through the 65-nm and 45-nm half-pitch nodes. However, he said, approaching the 32-nm node presents far greater challenges for the company, and so he described how IBM will tackle technological hurdles such as mask blank birefringence, pellicle apodization, EMF effects, and challenges in imaging optics.
The CEO of Molecular Imprints, Dr. Mark Melliar-Smith, then gave a captivated audience an overview of the promise of imprint lithography. Dr. Melliar-Smith described the basic history of imprint from its beginning in Chinese wax seals to today's polymerizing fluid with UV exposure. He then described in straightforward terms both the process of step-and-flash imprint lithography (S-FIL) and the recent progress that has been made on its many aspects.
One of the amazing benefits of the S-FIL process, Dr. Melliar-Smith indicated, is that it provides perfect replication. If you have a good template, you will have a good output, and there is no OPC. He showed that the process also draws from existing industries - templates use the same technology as photomasks to ensure commercial supply, and template repair builds on wafer inspection technology, using standard mechanical or e-beam additive or subtractive techniques.
He reported that the templates themselves are quite rugged, since Fused Silica is not eroded by the low-viscosity liquids used in the process. To prove this point, Dr. Melliar-Smith showed an example of a template purposely stamped onto a large particle on a base wafer. The template showed great resistance to damage in the experiment. Additionally, magnification control can be achieved by putting actuators completely around the template to squeeze it, giving the necessary adjustments.
In terms of throughput, Dr. Melliar-Smith state that the primary issue is fluid spread, although there are multiple contributors to throughput issues. It is essential that the material be acrylate-based, low-viscosity (< 10 cps), fast-curing (<400 msec), highly pure (<10 ppb ionics), etch-resistant, easily stripped, and, of course, compatible with CMOS. He showed that it is also helpful to optimize the template contact geometry by dropping the template at an angle. This allows the air between the pico-liter-sized drops to be swept out. The low cost of imprint heads also allows multiple heads to be installed on each tool to increase throughput.
Again, because every aspect of the technology - the tools, the materials, the process, and the template, all draw from existing technologies, Dr. Melliar-Smith predicts that imprint will be prepared for 32nm HP by 2010. However, some of the more interesting applications he described for the future of imprint technology were in different large markets. Specifically, he sees the imprinting of photonic crystals to create efficient, high-brightness LEDs and the etching of magnetic material into columns to advance hard disk drive (HDD) technology as markets with great use for imprint technology.