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SPIE Professional October 2008

FAB Expectations

ASML's chief scientist is optimistic that future semiconductor manufacturing will be "litho friendly" and that new technologies won't easily displace optical lithography as a driver for Moore's Law.

By Bill Arnold

In his 1959 talk, "There's Plenty of Room at the Bottom,"1 Richard Feynman offered $1000 to the first person who could demonstrate the ability to write the Encyclopedia Britannica on the head of a pin. This is equivalent to a linear scale reduction of 25,000X. The prize was claimed in 1986 by Tom Newman, a graduate student at Stanford University who used electron beam lithography to write the first page of "A Tale of Two Cities" in an area of only 5.9 × 5.9 microns.2 Feynman reportedly wrote Newman the check but quipped that he shouldn't cash it as his signature one day would be worth more.

Lithography has evolved from its use by artists such as Rembrandt, to eight-color postcards at the end of the 19th century, to high-resolution optical projection lithography which prints the world's most complex devices: microprocessors and memories.3 The stunning ability of lithography to image and build nanostructures has been the engine of worldwide expansion of the microelectronics business and the many fields it has revolutionized.

Moore's Law Persists

Gordon Moore predicted in 1965 that the density of silicon transistors on a chip would double every year,4 and in 1975 amended this to a doubling every 18 months.5 With only minor differences across a wide variety of devices, this incredible "law" has held for 43 years.

Moore's original devices were printed using masks cut from rubylith and projected with 16mm movie camera lenses purchased in a Northern California camera shop by Robert Noyce for a few hundred U.S. dollars.6 They had a minimum feature size of around 100 microns. Today the industry uses hyper-numerical-aperture water-immersion lenses which weigh nearly a half metric ton and cost several million dollars (U.S.) to resolve features as small as 37nm7 with light from a 60W argon fluoride excimer laser (193nm wavelength). See Figure 1.


Figure 1. Zeiss lens on ASML TWINSCAN machine.

Wafer step and scan systems ("scanners") can expose 30 or more mask levels on 300mm diameter silicon wafers at the rate of more than 100 wafers per hour. This represents an improvement in resolution of nearly 1000X and in pixel transfer rate of 1,000,000. However, another improvement of 1000X over the next 43 years will not spur the same progress in silicon devices since the limits dictated by atomic sizes will be reached (the lattice constant of crystalline silicon is 0.546 nm) and new device architectures and materials will have to evolve to allow further scaling.

The death of Moore's Law has been predicted for many years based on concerns for one or more perceived technical or economic limit. But it is a stubborn, persistent, and self-sustaining phenomenon, which allows both greater device performance and lower manufacturing costs per transistor with each advance in density. This in turn has enabled more sophisticated computational and manufacturing tools to be designed, funded, and built. The huge expansion of the microelectronics business has allowed the world's IC makers to build silicon chip factories (fabs) in the United States, Europe, and Asia. Worldwide revenues of the semiconductor industry are about $250 billion U.S. annually.

Memory Devices

In a similar vein, the demise of optical lithography is a perennial topic, starting at least 30 years ago at the 1 micron level, and continuing to today. A joke law among lithographers states that the death of optical lithography is always seven years away.8 However, only optical lithography offers the full package of fine resolution, nanometer-level overlay, and throughput rates high enough to sustain the cost-per- bit reduction rate required to continue Moore's Law. The giant capital investment in optical lithography and silicon manufacturing ensures that no new technologies can easily displace these true workhorses but rather must build on them and work with them in a complementary way.

CMOS silicon devices are expected to continue scaling to below 20nm, but there are many serious technical hurdles. Transistor device physicists identify the key issues as related to reducing gate dimensions and contacted interconnect pitch; finding new materials for gate insulators and electrodes; and control of dopants. CMOS transistors form the basis of all major types of integrated circuits, including microprocessors, dynamic random-access memory (DRAM), and flash memories.

Memories come in many different forms, which vary by read and write speed, volatility, and performance in different physical environments. Static RAMs (SRAMs) dominate high speed applications for on-chip cache for advanced logic devices. DRAMs dominate applications for high-speed (but power-hungry) computation. NAND flash memories are widely used for mobile, nonvolatile storage such as digital film and USB drives. These three memory types have unique device layout differences which result in characteristic lithography challenges. See Figure 2.


Figure 2.

Due to the relative simplicity of the NAND layout, it has been possible to scale this type of memory device faster than DRAM or SRAM, resulting in different rates of feature size reduction and increasing bit density. See Figure 3.


Figure 3. 

In memory technology there is significant pressure to scale faster than logic devices due to intense competition and staggering reductions in average selling price per year (typically ~40%). As a result, in recent years the density for NAND flash chips has doubled every year, allowing a new variant of Moore's Law to appear, Hwang's Law, named after C.G. Hwang of Samsung Electronics.9

In the event materials and patterning limits are reached, three dimensional memories that build bits vertically as well as laterally using existing technologies have become an important research direction for the large memory manufacturers as a potential way to continue increasing bit density, reduce cost per bit, and retain a small form factor.10-12 Memory technology has become the key driver for further improvements in lithography, and vice versa.

Litho-Friendly Circuits

Lithography has adapted itself to scaling requirements over the years, starting with symmetrical geometric scaling for bulk CMOS at feature sizes much greater than the wavelength of the exposure light. The limits of optical resolution in lithography are dictated by the Rayleigh equation (R = k1 λ/ NA), where k1 is a factor which measures the complexity of the process and has a limiting value of 0.25 for a single exposure, λ is the wavelength of the light and NA is the numerical aperture of the optics.13 As scaling has progressed, the feature sizes first became comparable to and then mere fractions of the exposure wavelength. As k1 decreases, contrast is lost in the image.

Resolution enhancement technology (RET) has evolved to bring back contrast even as device half pitch has continued to shrink. Common RETs employed include off-axis illumination and the use of phase shifting masks and the addition of sub-resolution assist features to mask features.14

Concerns for device performance variability in the face of statistical fluctuations in dopant concentrations and other effects such as line edge roughness at atomic scales, along with loss of image contrast, has led to notable changes in circuit layouts to make them more "litho-friendly" through drastic restrictions in design orientation and of line-space duty cycle. As the resolution limit of 193nm lithography is reached at about 37nm, double patterning has become the bridge to future device shrinks. In double patterning, critical mask levels are split into two or more masks. Each can be printed above the resolution limit but when combined, they achieve further density increase.15 Optical lithography keeps evolving to achieve ever more complex control over the nanoscape.

Cost Factor

Quantum computers were also forecast by Feynman,16 who asked "How small can you make a computer? … It turns out that we can make it pretty much as small as we want. … We can not get any smaller than atoms because we will always need something to write on, but all we actually need are bits which communicate. An atom, or a nucleus will do …."

Echoing these thoughts, Stephen Hawking puts technology limits to Moore's Law as probably dictated by "the speed of light and the atomic nature of matter."17 At the current rate of lithography scaling (~0.7X every two years), the industry will reach the length scale of atomic crystal lattices (order 1nm) by the mid 2040s.

Moore himself has often said he expects the law to be limited first by economics, including the rising cost of advanced lithography and new wafer fabs.18 The IC industry is undergoing a significant period of consolidation driven by the massive costs needed to develop and manufacture at smaller dimensions. Many former chipmakers have decided to go fabless and send their designs to foundries like TSMC or UMC in Taiwan; others have retained some internal capacity to make new generation parts but send most volume business to foundries for older generations (the "fablite" strategy). It is said that in five years only a few companies will still design and manufacture their own chips.

Likewise, in the lithography business, where there were 20 or more competitors in the early 1980s, there are only three left making the most advanced equipment (ASML BV of the Netherlands, and Nikon and Canon of Japan).

EUV and the Future

The lithography scanner business is sometimes likened to the aircraft industry where only Boeing and Airbus remain as the major suppliers. On the surface, the similarities are striking: massive capital equipment involving the highest technology available and unit sales on the order of 1000 per year. In the aircraft industry, the development of faster commercial jets stumbled with the Concorde and has now reached a stable period where subsonic craft such as the 777 and Airbus 380 lead future sales.

Industry experts wonder if lithography resolution has reached an economic limit with the introduction of EUV lithography. While most agree further resolution scaling is desirable and technically feasible, the big question is whether enough EUV photons can be generated and imaged in resist on wafers to meet the economic requirement of 100+ wafers per hour.

If this challenge is met, EUV lithography will eventually be the mainstream production process for devices down to the 10nm level.19 Reduction of wavelength coupled with higher NA lens designs may be possible to drive this further.


  • This is an open-access article from SPIE Professional, the SPIE member quarterly magazine. An SPIE member login is required to access the full text of other feature articles inside SPIE Professional magazine.
  • For a different view on the future of optical lithography, see a member-only article by Chris Mack.
References

1. R. P. Feynman, "There's plenty of room at the bottom," Engineering and Science, 1960.

2. Tom Newman, "Tiny tale gets grand," Engineering and Science, pp 24-26, January 1986.

3. John Bruning, "Optical Lithography: 40 years and holding," Proc. SPIE, Vol. 6520, pp 652004, 2007.

4. Gordon Moore, "Cramming more components onto integrated circuits," Electronics, Vol. 38, pp 114-117, April 1965.

5. Gordon Moore, "Progress in digital integrated electronics," IEDM Technical Digest, Vol. 21, pp 11-13, 1975.

6. Michael Riordan, "The silicon dioxide solution: how physicist Jean Hoerni built the bridge from the transistor to the integrated circuit," IEEE Spectrum, 2007.

7. W.H. Arnold, M.V. Dusa, J. Finders, "Metrology challenges of double exposure and double patterning," Proc. SPIE, Vol. 6518, pp 651802, 2007.

8. H.J. Levinson, W.H. Arnold, "Optical Lithography," Chapter 1, Handbook of Microlithography, Micromachining, and Microfabrication, ed. P. Rai-Choudhury, SPIE Press, p 13, 1997.

9. C.G. Hwang, "Nanotechnology enables a new memory growth model," Proc. of the IEEE, 2003.

10. Sandisk Matrix 3D; see http://www.news.com/Matrixs-3D-memory-chips-target-game-devices/.

11. S.M. Jung et al, "Three dimensionally stacked NAND flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30nm node," IEDM Technical Digest, 2006.

12. H. Tanaka et al, "Bit cost scalable technology with punch and plug process for ultra high density flash memory," Symp. on VLSI Tech. Dig., pp 14-15, 2007.

13. B.J. Lin, "Where is the lost resolution?" Proc. SPIE, Vol. 633, pp 44-50, 1986.

14. W.H. Arnold, "Overview of process equipment technology analyzed through the front-runner (3): Lithography technology," Nikkei Microdevices, pp 96-103, April 2006.

15. W.H. Arnold, "Toward 3nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography," Proc. SPIE, Vol. 6924, pp 692404, 2008.

16. R.P. Feynman, Feynman Lectures on Computation, A. Hey, R. Allen eds., Penguin Books, pp 182-183, 1996.

17. Jermey Matthews, "Semiconductor industry switches to hafnium-based transistors," Physics Today, pp 25-26, Feb 2008.

18. Gordon Moore, "Lithography and the future of Moore's Law," Proc. SPIE, Vol. 2439, pp 2-17, 1995.

19. W. Kaiser et al, "The future of EUVL," Proc. SPIE, Vol. 6924, pp 692405, 2008.


Bill Arnold
SPIE Fellow Bill Arnold is chief scientist at ASML US Inc. and will be a featured plenary speaker at the inaugural SPIE Lithography Asia Symposium in Taipei in November. His MS in physics is from the University of Chicago. He is one of several optical microlithography experts whose presentations at SPIE Advanced Lithography in February are captured in an SPIE.TV Webcast

Have a question or comment about this article? Write to us at SPIEprofessional@spie.org.

DOI: 10.1117/2.4200810.05

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