SPIE Startup Challenge 2015 Founding Partner - JENOPTIK Get updates from SPIE Newsroom
  • Newsroom Home
  • Astronomy
  • Biomedical Optics & Medical Imaging
  • Defense & Security
  • Electronic Imaging & Signal Processing
  • Illumination & Displays
  • Lasers & Sources
  • Micro/Nano Lithography
  • Nanotechnology
  • Optical Design & Engineering
  • Optoelectronics & Communications
  • Remote Sensing
  • Sensing & Measurement
  • Solar & Alternative Energy
  • Sign up for Newsroom E-Alerts
  • Information for:
    Advertisers
SPIE Startup Challenge 2015 Lead Sponsor - HAMAMATSU

CASIS

DSS Defense + Security | Call for papers

Gold Open Access option for SPIE Journals

SPIE PRESS




Print PageEmail Page

Defense & Security

Hot detectors

Composite array techniques combine flip-chip bonding and high-temperature processing methods to yield improved focal plane arrays.

From oemagazine June 2001
31 June 2001, SPIE Newsroom. DOI: 10.1117/2.5200106.0005

Designers of infrared imaging systems are increasingly turning to focal plane arrays (FPAs) as alternatives to the complexity and expense of optomechanically scanning linear array detectors to build up an image.1 An FPA consists of a two-dimensional array of detector elements, which are electrically connected to a silicon readout integrated circuit (ROIC) that performs the required signal conditioning and multiplexing.

The detector materials of interest tend to be complex compounds or require specialized high-temperature processing techniques that are not compatible with conventional ROIC fabrication and materials requirements. In addition, because of lattice mismatches, many detector materials need to be grown on epitaxial substrates such as GaAs or cadmium-zinc-telluride to obtain optimal performance. These conflicts with ROIC fabrication parameters have forced manufacturers to build hybrid arrays by separately processing the detector and the ROIC at a wafer level, then interfacing the diced chips using post-processing or back-end processing techniques such as flip-chip bonding.

Our group at the Defence Evaluation and Research Agency (DERA; Malvern, UK), in collaboration with BAE Systems (Southampton, UK), built a hybrid array by dicing a polished ceramic wafer of lead-scandium-tantalate (PST) and flip-chip bonding it to a complementary-metal-oxide-semiconductor (CMOS) readout chip using lead/tin solder bonds approximately 10 µm in diameter. A thin-film stack on the PST acted as both a resonant absorber of infrared radiation around 10-µm wavelength and as a common electrode. Separating the processing of the detector from that of the ROIC allowed us to process the PST ceramic at temperatures up to 1250°C to form a dense ceramic with excellent ferroelectric properties. Using this approach, we have fabricated arrays of up to 384 X 288 elements with good imaging capabilities.

integrated detector arrays

One drawback to the hybrid process is the fabrication cost, which involves processing chips singly rather than on a wafer-scale. Another problem--particularly for photon detectors, which require thermal cycling to low temperatures--is that thermal expansion mismatch between the detector and readout substrates limits array size. In the case of hybrid thermal detectors, the metallic bump-bond forms part of the thermal circuit of the detector structure. The bond acts as a thermal short to the silicon ROIC and therefore reduces the temperature rise in the ferroelectric detector element. Although this effect can be reduced by using small diameter bonds and by the addition of low thermal conductance polymers on the ROIC surface, the thermal design of the hybrid still limits imaging performance.

An attractive alternative to hybrid arrays is integrating the detector pixels with the ROIC during processing. Using thin-film ferroelectric detector materials in place of the bulk ceramic, DERA and BAE are developing integrated thermal detector arrays.2 We use surface micromachining to construct microbridge thermal isolation structures on the focal plane. The pixel structure is designed to achieve a high-radiation collection efficiency (fill-factor) and a high degree of thermal isolation from the substrate.

The design features a ferroelectric thin film patterned as a small capacitor block in the center of the pixel (see figure 1). The ferroelectric film is grown on a reflective electrode so that the stack acts as a resonant absorber at 10 µm. A thin dielectric/metal membrane forms the remainder of the bridge and provides a low thermal conductance connection to the ROIC. The novelty of this design lies in the fact that the bridge membrane extends across the pixel and acts as an extended-area radiation collector when combined with a reflective metal layer on the substrate.

Figure 1. The integrated ferroelectric detector pixel incorporates a microbridge structure to provide a high degree of thermal isolation for the ferroelectric thin film.

In addition to the thermal issues already mentioned, one of the limitations in the fabrication of integrated arrays is the thermal budget imposed by the ROIC. The processing temperatures for ferroelectric thin films are not as high as those for bulk material due to the template effects of the substrate, but high temperatures are still required to yield the best ferroelectric properties. The most obvious constraint imposed by the ROIC thermal budget is that the aluminum-copper-silicon metallization used in current CMOS processing melts at about 660°C. Even at lower temperatures, ROICs can suffer silicon diffusion, failure of barrier layers, and formation of hillocks that can punch through insulating layers.

CMOS ROICs are robust enough to handle moderate temperature increases, however. Thermal trials at DERA show that the circuitry can survive extended heating at 550°C in low- oxygen environments. BAE Systems has confirmed the compatibility of ROICs with repeated hotplate bakes at 520°C and has grown high-quality ferroelectric lead-zirconate-titanate (PZT) thin films within these temperature limits. The group has fabricated detectors on 6-in.-diameter ROIC wafers and produced 256 X 128-pixel integrated PZT detector arrays.

composite arrays

The ferroelectric ceramic material PST offers a factor of three increase in performance compared to PZT ceramic. This also is the case for PST thin films, but achieving this performance requires processing temperatures as high as 850°C, well in excess of the ROIC failure limits.3 To overcome thermal issues while gaining access to the high performance of PST thin films, we have developed a detector design that separates the high- temperature fabrication processes from the constraints of the readout circuitry. This composite array design combines elements of hybrid and the integrated array technology.

In composite array designs, low thermal conductance microbridge pixels are fabricated per the integrated technology; however, instead of being formed directly on the ROIC, they are formed on a high-density interconnect silicon wafer (see figure 2). The detector die are then flip-chip bonded to the ROIC die using the established hybrid array process, establishing an electrical connection to each element through a solder bond and conducting channel. The microbridges have a lower thermal conduction to the substrate and virtually no conduction between the pixels, yielding better sensitivity and spatial resolution than hybrid arrays. The key to the design is fabricating the high-density interconnect wafers using materials that can withstand high-temperature processing.

Figure 2. In composite array design, conducting through-wafer vias connect the microbridge detector pixels to the readout chip.

The composite array design brings other benefits for detector array fabrication. The interconnect wafers can be a different size than the ROIC wafers, obviating the need to tool the post- processing to match the large diameter foundry wafers. The only required post-process is adding the flip-chip interconnect bonds to the ROIC, which means that engineers are free to choose any readout design and ROIC manufacturer.

The high-density interconnect wafer requires through-wafer vias in the silicon on a pitch equal to the detector pixel pitch. The vias must be lined with insulator, then filled with conductive material to form the conducting link to the readout. To aid fabrication, the wafer thickness should be compatible with standard silicon wafer-processing equipment.

The group at DERA has demonstrated interconnect wafer fabrication steps using a 380-µm-thick, 100-mm-diameter silicon wafer. We formed vias with an anisotropic silicon etch-process system and achieved high aspect ratio using sulfur hexafluoride/octafluorocyclobutane (SF6/C4F8) etch-passivation cycles in an ICP reactive-ion etcher.4 The etching process required five hours per wafer. We lined the vias with high- temperature insulator and conductor materials, giving a via resistance around 100 Ω. The completed wafers withstood processing temperatures up to 1000°C. We observed no compromise in wafer strength, even when fabricating 20 or more 384 X 288 arrays per wafer, which represents more than two million vias.

Composite array designs allow designers to construct pixel structures using standard thin-film processes while taking advantage of high-temperature detector processing. Test results on mechanically assembled composite arrays look encouraging. We expect the first imaging demonstration of 384 X 288 element composite PST arrays later in the year. oe

Acknowledgments:

This work was funded by the UK Ministry of Defence. Published with the permission of DERA on behalf of the Controller of HMSO. British Crown Copyright 2001/DERA.

References

1. P Norton et al. Proc. SPIE 4130, pp. 226-236 (2000).

2. R. Watton and P. A. Manning, Proc. SPIE 3436, pp. 541-554 (1998).

3. M. A. Todd et al. Proc. SPIE 4130, pp. 128-139 (2000).

4. J. K. Bhardwaj and H. Ashraf, Proc. SPIE 2639, pp. 224-233 (1995).


Michael Todd
Michael Todd is with DERA, St. Andrews Road, Malvern, UK.
Andy Parsons
Andy Parsons is with BAE Systems Infra-Red Ltd., Caswell, England.