• Conference Proceedings
  • Journals
  • Journal of Applied Remote Sensing
    Journal of Astronomical Telescopes, Instruments, and Systems
    Journal of Biomedical Optics
    Journal of Electronic Imaging
    Journal of Medical Imaging
    Journal of Micro/Nanolithography, MEMS, and MOEMS
    JM3 Information for Authors
    Journal of Nanophotonics
    Journal of Photonics for Energy
    Optical Engineering
    Individual Subscriptions
    Institutional Subscriptions
    SPIE Journals on CD-ROM
  • SPIE Digital Library
  • Books
  • Collections
  • Open Access
  • Contact SPIE Publications
Print PageEmail Page

Journal of Micro/Nanolithography, MEMS, and MOEMS Special Sections

To submit a manscript for consideration in a Special Section, please prepare the manuscript according to the journal guidelines and use the Online Submission SystemLeaving site. A cover letter indicating that the submission is intended for this special section should be included with the paper. Papers will be peer‐reviewed in accordance with the journal's established policies and procedures. Authors who pay the voluntary page charges will receive the benefit of open access.

View the list of special sections that have already been published on the SPIE Digital Library.

Calls for Papers:

Holistic/Hybrid Metrology

Continuation of Scaling with Optical and Complementary Lithography

Control of Integrated Circuit Patterning Variance Part 1: Metrology, Process Monitoring, and Control of Critical Dimension

October-December 2014

Holistic/Hybrid Metrology

Guest Editors:

Alok Vaid
400 Stonebreak Road Extension
Malta, New York 12020
E-mail: Alok.Vaid@GLOBALFOUNDRIES.com

Eric Solecky
IBM Systems and Technology Group
Route 52
Hopewell Junction, New York 12533
E-mail: solecky@us.ibm.com

Call for Papers: Metrology has played a key role in enabling integrated circuit mass production, as well as a wide range of MEMS and MOEMS devices. Introduction of new material stacks, shrinking design rules, and complex 3-D architectures in semiconductor technology has led to major metrology challenges by posing stringent measurement performance requirements for various critical dimensions, feature shape dimensions, and geometrical attributes. To provide an overview of the most recent developments, this special section provides a forum for reports on new techniques and advances in metrology methods for semiconductor integrated circuits, MEMS, optics, and photonics at the micro- and nanoscales.

To address the challenges arising from advanced fabrication technologies, we invite overview and original papers describing current and expected challenges along with potential solutions for applications. A special topic is introduced this year called "holistic metrology," also known as hybrid metrology, and closely linked to virtual metrology. Topics of interest include, but are not limited to, the following:

  • Combining multiple measurement techniques virtually or physically into a single platform
  • Combining a multitude of measurement data from multiple metrology platforms and impact on measurement uncertainty
  • Use(s) of the integrated measurement data in lot disposition and/or automated process control
  • Use of process or equipment data to improve measurement performance
  • Limits of conventional techniques and the need for hybrid metrology
  • Standards required to implement hybrid metrology across fabs
  • Understanding fundamental physics of conventional techniques and their synergies when combining.

Closed for submissions.


January-March 2015

Continuation of Scaling with Optical and Complementary Lithography

Guest Editors:

Kafai Lai
IBM Semiconductor R&D Center
2070 Rt. 52
Hopewell Junction, New York 12533
E-mail: kafailai@us.ibm.com

Andreas Erdmann
Fraunhofer Institute for Integrated Systems and Device Technology
Technology Simulation Department
Schottkystr. 10
Erlangen 91058 Germany
E-mail: andreas.erdmann@iisb.fraunhofer.de

Call for Papers: While EUV lithography is still maturing, optical lithography is expected to continue as the primary lithographic technology for manufacturing over the next several years. Extension of water-based immersion lithography to below 20-nm half-pitch (10-nm logic node) requires the use of innovative resolution enhancement techniques, solutions to complexities introduced by hyper-NA optics, and extensive use of double or multiple sequential exposure and patterning techniques, and even complementary use of optical lithography with nontraditional techniques. In addition to resolution, very tight process (and overlay) control and high-quality photomasks are also necessary. The successful use of optics to provide viable working solutions for these device nodes will require fundamental integration of all aspects of the patterning process. The cost of advanced lithography is another concern that is in need of creative solutions, such as "freezing" the first resist in double patterning approach and the use of directed self-assembly in optically created guiding patterns. For 14-nm and beyond, early design technology co-optimization is necessary to ensure the patterning solution can enable design for products. This special section welcomes paper submissions covering topics that advance the field of optical nano- and microlithography that extend optical lithography beyond the 14-nm technology node and enable circuit scaling.

In addition to scaling in the horizontal direction, vertical scaling is becoming a way to maintain Moore's law of device scaling through the use of advanced imaging and overlay techniques for 3-D wafer integration. Furthermore, "More than Moore" scaling for non-very large scale integration (VLSI) applications is gaining much momentum in industry application and academic research. Novel techniques like 3-D imaging/printing as well as optical microsculpturing recently provided versatile applications beyond the electronic industry. Papers on such patterning topics using optics are welcome as well.

Suggested topics for this special section include (but are not limited to) the following:

Pushing the Limits of 193-nm Optical Lithography

  • Innovative optical methods to break diffraction limit
  • Holographic lithography
  • Multiple-exposure and double-masking techniques, including requirements and challenges of cut-mask 
  • Layout optimization to extend the limits of optical lithography
  • Design compliance towards multiple patterning/self-aligned double patterning
  • Process issues for pitch splitting 
  • Mask topography effects associated with hyper-NA imaging
  • Laser bandwidth, source fidelity, apodization, and other effects
  • Implementation and integration of resolution-enhancement methods
  • Optical lithography at k1 < 0.3 
  • Proximity effect characterization, correction, and control
  • Source and mask optimization (SMO)
  • Inverse lithography technology (ILT)

Complementary Lithography

  • Enhancement of optical lithography by emerging new material and processing techniques: directed self assembly, two-photon absorption materials, and optical metamaterials
  • Combination of different exposure techniques including projection, multiple-beam interference, and holographic lithography
  • Combination of exposures at different wavelengths or with electrons
  • General design, processing, and metrology challenges

Advanced Computational Lithography

  • Advanced mask decomposition for multiple patterning
  • Advanced pattern correction and verification
  • Rigorous and compact modeling of optical and process effects
  • Advanced compact model verification and calibration techniques
  • Source, mask, pupil, and target co-optimization
  • High-performance computing environment for computational lithography
  • Advanced pattern selection and matching methods
  • Mask writing shot counts minimization for advanced resolution enhancement technology (RET)

Design Technology Co-optimization

  • Advanced ground rules methodologies
  • Innovative design flow for multiple patterning and nontraditional patterning techniques
  • Systematic discussion of process-induced design restriction's impacts to design
  • Unidirectional designs with cut masks to reduce patterning complexity
  • Advanced retargeting of designs

Multiple Patterning Process Integration

  • Multiple exposure and double masking techniques, including requirements and challenges of cut-mask 
  • Multiple-patterning process integration issues such as etch and thin-film deposition
  • Advanced mask-type optimization
  • Advanced processing steps including negative tone development process, resist freezing, etc.

Pushing Lithography Tools and Subsystems

  • Innovative subsystems to push for nanometer scale alignment and overlay
  • Process optimization for improving product overlay
  • Advanced monitoring and optimization algorithms to minimize critical dimension (CD) variation
  • Innovative scanner optics design and manufacturing
  • Advanced in-situ metrology for tool control
  • High-performance excimer laser sources.

Manuscripts due 1 September 2014.


January-March 2015

Control of Integrated Circuit Patterning Variance Part 1: Metrology, Process Monitoring, and Control of Critical Dimension

Guest Editors:

Alexander Starikov
I & I Consulting
2215 Greer Road
Palo Alto, California 94303-3129
E-mail: alstarikov@gmail.com

Matthew Sendelbach
Nova Measuring Instruments, Inc
2055 Gateway Place, Suite 470
San Jose, California 95110-1019
E-mail: matt-se@novameasuring.com

Call for Papers: Control of device dimensions is conventionally defined as consisting of two complementary components assumed to be independent: image size [critical dimension (CD)] and image placement [registration, alignment, and overlay (OL)]. Two kinds of dimensional metrology are practiced, typically on different tools, with process corrections applied in two separate control loops. Although pattern doubling leads to intermix of CD and OL budget components, at the process level, the physical mechanisms driving size variations are different from those in placement errors. Even though it already is hard to define what constitutes pattern size and placement in processed devices, and despite some process interactions causing correlated CD and OL variation, the old paradigm for control of device dimensions is still the "process of record."

This special section of the Journal of Micro/Nanolithography, MEMS, and MOEMS seeks to offer comprehensive technology overviews, in-depth accounts of the latest technologies, applications methods and capabilities in process-related metrology, as well as monitoring and inspection primarily related to control of patterned device size (critical dimension). A complementary special section on metrology and control of image placement, including correlated CD and OL components of device pattern variance, is planned for January–March 2016.

The field of CD-related metrology and process control went through a period of rapid change that lasted a decade, if not longer. New metrology applications for direct estimation, monitoring, and control of key process parameters, such as exposure dose and focus in lithography, have emerged. Highly capable, and much more efficient than conventional CD metrology, process monitors support superior process control and tighter process windows. This new approach to metrology and process control has enabled optical microlithography extensions to device half-pitch close to the 0.25λ/NA limit (where λ is the exposure wavelength, and NA is the numerical aperture) and even beyond (with process-driven pattern multiplication). What used to be the "off the Roadmap metrology" is now a part of today's mainstream in-FAB process control practice. Inspection of across-wafer process variation has also emerged. Yet, this is still a young and rapidly evolving field, with little consensus on technology direction, preferred solutions, and performance requirements for standalone and integrated metrology, as well as for process equipment.

Please submit a technology overview, a consolidation of earlier work presented at various venues, or an original technical paper describing this field. Topics of interest include, but are not limited to, the following:

Methods, technologies, and applications for control of device variance

  • Sources of device size variations, their signatures in space and time
  • Downstream impacts of pattern shape, size, height, and roughness
  • Pattern size modifiers such as stress, carrier mobility, interface properties
  • Performance and e-test versus in-line measurement of size and materials properties
  • Modeling, predicting, and in-line control of device characteristics
  • Correlation of process parameters to CD variance, e-test, performance, and yield
  • Segmentation of device variance and control of its principal components
  • Environmental and incoming variation, adaptive control, and feed forward
  • Tool, process, and integrated variance, characterization, and control
  • Process control versus product quality assurance and compliance validation
  • Design and process integration for efficient high-volume manufacturing

Metrology and process control in lithography and etch (patterning)

  • Integrated metrology and sensors for tool, process, and product control
  • Standalone metrology for process control and product quality assurance
  • SEM, optical microscopy, and scatterometry-based methods
  • Performance requirements, matching, accuracy, and calibration
  • Across-technology metrology comparisons and hybridization
  • Model and experiment-based monitors of process parameters
  • Test structures versus product; test wafer versus on-product metrology and control
  • Metrology structures, design for performance, and metrology integration
  • Metrology and control of film thickness, stress, carrier mobility

Inspection of process variation

  • Inspection for patterning defects versus inspection for process variation
  • Inspection of across-wafer and across-mask variation of CD, sidewall, or depth
  • Inspection and metrology for equipment and process characterization
  • Performance and applications of process inspection-based methods
  • Identifying and controlling the ubiquitous systematic yield losses
  • Technology outlook: how to control everything while still making a profit.

Manuscripts due 15 July 2014.


Published Special Sections:

Alternative Lithographic Technologies III (July-September 2014)
Guest Editors: Douglas J. Resnick, Christopher Bencher, and Ricardo Ruiz

Metrology and Inspection for 3-D Integrated Circuits and Interconnects (January-March 2014)
Guest Editors: Yi-sha Ku and Alexander Starikov

Emerging MOEMS Technology and Applications (January-March 2014)
Guest Editors: M. Edward Motamedi, Joel Kubby, Patrick Ian Oden, and Wibool Piyawattanametha

Optical Lithography Extension Beyond the 14-nm Node (January-March 2014)
Guest Editors: Will Conley and Kafai Lai

Advanced Fabrication of MEMS and Photonic Devices (October-December 2013)
Guest Editors: Georg von Freymann, Mary Ann Maher, and Thomas J. Suleski

Advanced Plasma-Etch Technology (October-December 2013)
Guest Editors: Ying Zhang, Qinghuang Lin, and Gottlieb S. Oehrlein

Alternative Lithographic Technologies (July-September 2013)
Guest Editors: Will Tong and Douglas J. Resnick

Photomasks for EUV Lithography (April-June 2013)
Guest Editors: Christopher J. Progler and Frank E. Abboud

Alternative Lithographic Technologies (July-September 2012)
Guest Editors: William M. Tong, Douglas J. Resnick, and Benjamin Rathsack

Directed Self-Assembly (July-September 2012)
Guest Editors: Daniel P. Sanders and William H. Arnold

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS III (April-June 2012)
Guest Editors: Sonia M. García-Blanco and Rajeshuni Ramesham

EUV Sources for Lithography (April-June 2012)
Guest Editors: Vivek BAkshi and Anthony Yen

Dimensional Metrology with Atomic Force Microscopy: Instruments and Applications (January-March 2012)
Guest Editors: Ronald Dixson and Ndubuisi G. Orji

Theory and Practice of MEMS, NEMS, and MOEMS (January-March 2011)
Guest Editor: Yu-Cheng Lin

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS II (October-December 2011)
Guest Editor: Rajeshuni Ramesham

Line-Edge Roughness (October-December 2011)
Guest Editors: Chris A. Mack and Will Conley

Metrology (October-December 2011)
Guest Editors: Moshe Preil and Shaunee Cheng

BioMEMS, Theory and Practice of MEMS/NEMS, and Sensors (July-September 2010)
Guest Editor: Yu-Cheng Lin

Extreme-Ultraviolet Lithography (October-December 2009)
Guest Editors: Kevin Cummings and Kazuaki Suzuki

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS (July-September 2009)
Guest Editors: Rajeshuni Ramesham and Allyson L. Hartzell

Computational Lithography (July-September 2009)
Guest Editors: Donis Flagello and Chris Mack

Theory and Practice of MEMS/NEMS/MOEMS, RF MEMS, and BioMEMS (April-June 2009)
Guest Editor: Yu-Cheng Lin

Extreme-Ultraviolet Interference Lithography (April-June 2009)
Guest Editor: Franco Cerrina

Double-Patterning Lithography (January-March 2009)
Guest Editor: William H. Arnold

Silicon-Based MOEMS and Their Applications (April-June 2008)
Guest Editors: Harald Schenk and Wibool Piyawattanametha

Resolution Enhancement Techniques and Design for Manufacturability (July-September 2007)
Guest Editor: Alfred K. K. Wong

Bio-MEMS and Microfluidics (April-June 2006)
Guest Editors: Wanjun Wang and Ian Papautsky

Nanopatterning (January-March 2006)
Guest Editors: Kees Eijkel, Jill Hruby, Glen Kubiak, M. Scott, Volker Saile, and Steven Walsh

MOEMS Design, Technology, and Applications (October-December 2005)
Guest Editor: M. Edward Motamedi

Polarization and Hyper-NA Lithography (July-September 2005)
Guest Editor: Donis Flagello and Christopher J. Progler

Next Generation Lithography (January-March 2005)
Guest Editor: Walt Trybula

Mask Technology for Optical Lithography (April-June 2004)
Guest Editor: Kevin D. Cummings and Frank M. Schellenberg

Immersion Lithography (January-March 2004)
Guest Editor: William H. Arnold

Surface Micromachining (October-December 2003)
Guest Editors: Jeffry J. Sniegowski and James H. Smith

Micro-Optics for Photonic Networks (October-December 2003)
Guest Editor: Thomas J. Suleski

Lithography for Sub-100-nm Device Fabrication (October-December 2002)
Guest Editor: William H. Arnold

Author Tools

Prepare a Manuscript
Copyright Forms
Code of Ethics
Publication Charges
Journal Policies
Open Access