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FORTHCOMING SPECIAL SECTIONS:
Photomasks for EUV Lithography
Directed Self-Assembly
EUV Sources for Lithography
Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS III
Dimensional Metrology with Atomic Force Microscopy: Instruments and Applications
Photomasks for EUV Lithography
Guest Editors:
Christopher J. Progler
Photronics, Inc.
601 Millennium Drive
Allen, Texas 75013
E-mail: cprogler@photronics.com
Frank E. Abboud
Intel Corp.
2200 Mission College Boulevard
Santa Clara, California 95054-1537
E-mail: frank.e.abboud@intel.com
Call for Papers: EUV lithography continues to make great strides as a next-generation candidate to pattern the most advanced semiconductor devices. While the industry shows support for the technology through investment in pilot and initial production systems, many technical hurdles remain on the road to cost-effective, high-volume EUV manufacturing. This special section will serve to address the critical challenges and progress in development, manufacturing, and use of EUV photomasks for integrated circuit manufacturing. Submissions targeting a broad range of relevant topics are solicited including, but not limited to, the following:
• EUV mask process module development (write, etch, clean, inspect, repair)
• Mask lifetime, damage, and degradation mechanisms
• EUV specific mask equipment technology and applications
• Mask blank technology from starting material to finished substrate
• Development and performance of EUV mask resists and layers
• Optimization of mask bulk materials and parameters (films, absorbers, buffers)
• EUV mask tolerances (registration, CD, 3D pattern fidelity, defects)
• Interaction of mask parameters and topography with wafer lithography printing
• Development of new mask types (phase shift, high transmission, dose optimized)
• Mask defect characterization and mitigation
• Mask quality validation and in-process checking/cleaning
• Mask handling, protection and storage
• Mask modeling and pattern correction or compensation methods
• Logistics and challenges in mask fab to wafer fab product flow
• Optimum design of EUV mask lines for efficiency, yield, and cycle time
• Use case strategies for EUV masks (critical layers, contacts, line cutting)
• Application specific considerations (memory, MPU, foundry, ASIC, shuttle)
• Mask processing cost and yield modeling and validation
All papers will undergo the standard JM3 peer-review process. Manuscripts should be submitted to SPIE according to the journal guidelines. A cover letter indicating that the submission is intended for this special section should be included. For more information, please contact the guest editors or jm3@spie.org.
Manuscripts due 1 September 2012.
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July–September 2012
Directed Self-Assembly
Guest Editors:
William H. Arnold
ASML
8555 South River Parkway
Tempe, Arizona 85284
E-mail: bill.arnold@asml.com
Daniel P. Sanders
IBM Almaden Research Center
650 Harry Road
San Jose, California 95120
E-mail: dsand@us.ibm.com
Traditionally, shrinking feature sizes through high-resolution lithography has propelled the semiconductor industry by increasing device density while simultaneously reducing fabrication costs per transistor. The semiconductor industry has resorted to double patterning techniques to extend the capabilities of single-exposure 193-nm immersion lithography while attempting to solve the remaining technical issues with next-generation lithographies (NGLs) such as extreme ultraviolet (EUV) lithography. However, extending double patterning techniques to achieve even higher levels of pitch multiplication (tripling or quadrupling) comes with considerable increases in process complexity and costs of ownership. While the semiconductor industry is focused on a NGL that will fulfill its particular set of requirements, its proposed higher resolution patterning solution may be unsuitable for other industries (e.g., hard disk drive), which are bound by different timing, performance, and economic constraints. Directed self-assembly (DSA) has been proposed as a potential “bottom-up” technology to augment or extend the capabilities of traditional and next-generation “top-down” lithography and overcome limitations with respect to resolution, uniformity, process complexity, and throughput. In particular, many promising capabilities of block copolymer-based DSA, including the ability to make sublithographic features with feature multiplication/interpolation, have been published in the last decade. In recent years, researchers have begun exploring the potential use of DSA in the fabrication of nanoimprint templates, displays, and semiconductor devices; however, much is still unproven and unknown regarding the capabilities (and limitations) of DSA as a practical nanofabrication technology. This special section of JM3 will include papers focusing on the performance, potential applications, and challenges of DSA as a practical lithographic technology for nanofabrication. DSA-related papers were solicited in the following areas:
• Applications of DSA in nanofabrication
• Novel DSA materials (block copolymers, hybrids, etc.)
• Orientation control and integration strategies and materials
• Novel wafer processing techniques
• Dry and wet development and pattern transfer processes
• LER/LWR, CD uniformity, defectivity, and other performance evaluations
• Metrology requirements and solutions
• Computational simulation of DSA materials and processes
• Layout and design considerations.
Closed to submissions.
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April–June 2012
EUV Sources for Lithography
Guest Editors:
Vivek Bakshi
EUV Litho, Inc.
10202 Wommack Road
Austin, Texas 78748
Tel: 512-462-2290
E-mail: vivek.bakshi@euvlitho.com
Anthony Yen
Taiwan Semiconductor Manufacturing Company
168, Park Avenue 2, Hsinchu Science Park
Hsinchu County, Taiwan 308-44
Tel: +886 3 5636688
E-mail: tony_yen@tsmc.com
EUV lithography (EUVL) is a leading candidate of next-generation-lithography technologies for high-volume manufacturing (HVM) of semiconductor devices. At present, EUVL alpha tools have been in the field for a number of years and beta tools have largely been delivered while work continues to develop HVM scanners. Metrology tools for supporting EUV mask metrology also are being developed. EUV sources have presented the leading technical challenges for developing scanners and metrology tools for EUVL. Sources will require increasing average power and higher brightness to support EUVL scanners and metrology tools. To address these urgent topics, we invite technical papers describing current and expected issues that limit EUV source technology. Both theoretical and experimental papers will be featured in these areas:
• Laser produced plasma (LPP)
• Discharge produced plasma (DPP)
• Alternative approaches to generating EUV photons
• Existing sources operating at wavelengths of 13.5 nm
• Beyond EUV (BEUV) sources at wavelengths of 6.x nm
Recommended topics include:
• Technology limits and challenges of high-power EUV sources
• Technology limits and challenges of low-average-power, high-brightness sources for EUV mask metrology
• Modeling and atomic databases needed to support modeling of EUV sources
• Collector optics, spectral purity filters, and high-power lasers for EUV sources
Closed to submissions.
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April–June 2012
Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS III
Guest Editors:
Sonia M. García-Blanco
University of Twente
P.O. Box 217
7500 AE Enschede
The Netherlands
Tel: +31 53 489 4768
E-mail: s.garciablanco@utwente.nl
Rajeshuni Ramesham
Jet Propulsion Lab
4800 Oak Grove Drive
Pasadena, California 91109
Tel: 818-354-7190
E-mail: rajeshuni.ramesham@jpl.nasa.gov
The purpose of this special section is to provide a technical stage to publish recent advances made in reliability, packaging, testing, and characterization of microelectromechanical systems (MEMS) and micro-optoelectromechanical systems (MOEMS) for various applications. High-quality papers on the following topics were solicited:
- Packaging process reliability, including packaging materials, assembly processes, bonding materials, wafer-level packaging, high-vacuum packaging, hermeticity, leak testing, new testing tools to monitor hermeticity, thin-film getters and activation techniques, packaging without hermeticity, MEMS assembly cleanroom science, issues in integration of MEMS/MOEMS andICs/ASICs/FPGAs, nondestructive evaluation of packaged systems (x-ray, acoustic microscopy, IR), effects of extreme and harsh environments (low and high temperature, radiation, shock, vibration),commercial-off-the-shelf (COTS) solutions, simulations/models, lead-free solder, and predictions of life of packaged MEMS systems
- BEOL process reliability issues, including production and yield improvement, yield improvement by reducing stiction, parametric test methods and/or test structures used to assure fabrication processes, release methods and techniques, yield modeling and process control methodologies
- Reliability methodology, including aging, dormancy, early life failures, accelerated life testing, predictive models, acceleration factors, design of experiments, physics of failure, reliability in design, measurement techniques and properties, data reduction and visualization, scaling issues, reliability tool development, automation, and device/system reliability
- Reliability of surfaces, including stiction, adhesion, lubrication, critical point drying methods, self-assembled monolayers (SAMs) or other coating materials, tribology, surface molecular contamination, particulate contamination, and contact resistance· Reliability of materials, including fracture, static and cyclic fatigue, wear, and life-cycle predictability
- Testing methods, including qualification of devices or systems, environmental testing (shock, vibration, temperature extremes, humidity, power cycling, contact cycling), highly accelerated lifetime testing (HALT), verification, and automation
- Standards development, including testing and measurement standards of devices or MEMS materials properties
- Characterization methods, including metrology tool development, laser Doppler vibrometry, interferometric methods, confocal microscopy, automation, calibration, and comparison to models
- Failure analysis, including identification of failure modes and mechanisms, novel analysis techniques, novel tools, and case histories
- Reliability of MEMS for space applications and devices for space applications
- Packaging and integration technologies for MOEMS, MEMS, and NEMS.
The scope of this special section includes all new and interesting aspects of reliability, packaging, testing, and characterization of MEMS and MOEMS. Articles based on theoretical, experimental, and simulation results were considered for publication.
Closed to submissions.
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January–March 2012
Dimensional Metrology with Atomic Force Microscopy: Instruments and Applications
Guest Editors:
Ronald Dixson
National Institute of Standards and Technology
100 Bureau Drive, Stop 8212
Gaithersburg, Maryland 20899
Tel: 301-975-4399
E-mail: Ronald.dixson@nist.gov
Ndubuisi G. Orji
National Institute of Standards and Technology
100 Bureau Drive, Stop 8212
Gaithersburg, Maryland 20899
Tel: 301-975-3475
E-mail: Ndubuisi.orji@nist.gov
The use of atomic force microscopy (AFM) for dimensional metrology of nanostructures has increased steadily during the last two decades. Starting in the 1990s, the national metrology institutes of several nations began to develop AFM instruments that incorporated displacement interferometry to achieve intrinsic traceability to the International System of Units (SI) meter. On the industrial side, the advent of critical-dimension AFM overcame the tip-related limitations of conventional AFM on near-vertical structures—making it possible to bring linewidth reference metrology to the fabrication floor. This special section will be comprised of the following three subtopical areas:
1. instrumentation and design for metrological AFM systems,
2. traceable metrology and calibration strategies using AFM,
3. reference measurements and in-line applications of AFM for manufacturing metrology.
Closed to submissions.
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