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Lithography Integration for Semiconductor FEOL & BEOL Fabrication (SC992)

Course Level: Introductory
Instructor: Qinghuang Lin, Ying Zhang, IBM Thomas J. Watson Research Ctr. (United States)

Course Details

Semiconductor fabrication, traditionally including Front-End-Of-The-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact (CA) formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The state-of-the-art semiconductor chips, the so called 14 nm node of Complementary Metal–Oxide–Semiconductor (CMOS) chips, in mass production features a second generation three dimensional (3D) FinFET, a metal one pitch of about 55 nm and copper (Cu)/low-k (and air-gap) interconnects. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor fabrication flow, its integration schemes, fabrication processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process and integration engineers a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high-K/metal gate or HKMG, III-V materials), new device and interconnect structures (such as FinFET/ Trigate, nanowires, Cu/air-gap interconnects) and new integrations (such as 3D IC, Through-Silicon Via or TSV) as well as recent lithography innovations (such as double patterning and directed self-assembly, DSA).

Learning Outcomes

This course will enable you to:

  • acquire the critical concepts of modern semiconductor on-chip fabrication flow
  • review semiconductor technology trends
  • evaluate the basic concepts of FEOL/MOL/BEOL integration flow
  • describe the basic processes of FEOL, including isolation, well doping, gate patterning, spacer, silicides and dual stress liner formation
  • identify the advanced patterning technology for scaling CMOS
  • describe how new materials and 3D COMS devices pose new challenges for lithography
  • identify the challenges and interactions between lithography and all the critical processes
  • describe BEOL copper/low-k dual damascene integration schemes
  • describe the basic processes used to fabricate dual damascene copper/low-k BEOL
  • examine the technical challenges in extending copper/low-k BEOL and Cu/air-gap interconnect integration
  • describe the basics of airgap interconnects, double patterning and DSA
  • review the unique requirements for BEOL lithography
  • develop lithographic materials and integration strategies for FEOL/MOL/BEOL patterning
  • demonstrate practical techniques for FEOL/MOL/BEOL lithography processes
  • examine recent innovations in semiconductor technology, including Cu/air-gap interconnects, HKMG, FinFET, III-V, Nanowires, Double Patterning, DSA, 3D IC and TSV etc.
Intended Audience

This course is designed for engineers, technicians, and managers in FEOL/MOL/BEOL lithography development and manufacturing; scientists, engineers, managers, and technical support; and marketing and sales personnel of FEOL/MOL/BEOL lithographic material suppliers. It is also intended for those who have a general interest in semiconductor fabrication processes.

Instructor

Qinghuang Lin is a Research Staff Member, a manager and an IBM Master Inventor at IBM T.J. Watson Research Center. For more than15 years years, he has held positions in photoresist development, advanced lithography, BEOL materials & integration, 3D integration and semiconductor technology strategy for several nodes of CMOS technology research and development at IBM. He holds more than 70 issued and pending US patents. Dr. Lin is the editor of 2 books and 6 conference proceedings, and the author and co-author of over 60 technical papers. He is a co-recipient of a 2002 IBM Research Division Achievement Award for "invention, development and implementation of 248 nm bilayer resist technology in manufacturing." He chaired the SPIE Conference on Advances in Resist Materials and Processing Technology from 2006-2007. He is conference chair of China Semiconductor Technology International Conference held at SEMICON China 2012 and 2013. Currently Dr. Lin serves as an associate editor of Journal of Micro/Nanolithography, MEMS and MOEMS (JM3) and as the Secretary of the Division of the Polymeric Materials of the American Chemical Society.

Ying Zhang is a Technical Director with Taiwan Semiconductor Manufacturing Company (TSMC) currently working in plasma etching area. Prior to joining TSMC, he was a Research Staff Member and the manager of the Advanced Plasma Processing and Metallization group at the IBM T.J. Watson Research Center. He worked on plasma processing for advanced microelectronics, including many nodes of CMOS technology development and exploratory nanometer scale novel device prototyping beyond the CMOS era.


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