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Micro/Nano Lithography

Joseph Sawicki: Making the Impossible -- Dealing with Patterns Throughout the Design and Manufacturing Flow

A plenary presentation from SPIE Advanced Lithography 2014

23 April 2014, SPIE Newsroom. DOI: 10.1117/2.3201402.03

We have always described a semiconductor process node by aspects of pitch. Whether it is a minimum channel length, metal spacing, or as seems more common now, a number driven by the marketing department's target message, everything came down to widths and spaces. Regardless of how we got there, this matched well with both design and manufacturing views up though about 130nm. For designers, smaller transistors, and smaller interconnect pitches mapped to faster, smaller, and cheaper designs. For the fab, the widths and spaces mapped directly onto particle-defect densities and defined their yield challenge.

The world started to change somewhere in the 130nm to 90nm timeframe. Driven by the well-known difficulties involved in lithography and exacerbated by increased sensitivity in processes like CMP, design-style-based or systematic defects became the major challenge to yield ramp, adding to the basic process ramp. Because of its involvement in the design, manufacturing, and test, EDA is in a unique position to contribute toward controlling, if not solving, the problem. This talk looks at:

  • Solutions in the DFT space that let us identify pattern failures hiding in yield loss
  • New methods in OPC that allow for process window expansion of problematic hot spots
  • Upcoming modeling technologies that target new pattern failure mechanisms in emerging nodes
  • New tools in the design spaces that can give designers visibility into the risks of production.

The goal is a pattern-aware EDA flow that minimizes risk, enhances manufacturing and quickly finds issues when they occur.

Joseph Sawicki is the vice president and general manager of the Design-to-Silicon division at Mentor Graphics. An expert in IC nanometer design and manufacturing challenges, Sawicki is responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line. Sawicki joined the company in 1990 and has held previous positions in applications engineering, sales, marketing and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.