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Journal of Micro/Nanolithography, MEMS, and MOEMS

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Micro/Nano Lithography

Flexible transparent devices from bulk silicon (100)

A generic batch process transforms conventional silicon electronic circuits into flexible, semi-transparent devices.
18 November 2013, SPIE Newsroom. DOI: 10.1117/2.1201311.004863

Flexible electronics is a promising field that has the potential to expand uses for both digital and analog devices. However, the new circuits have yet to match the performance, functionality, and cost-effectiveness of their conventional rigid counterparts.1–8  The application of flexible electronics in computation, communication, navigation, and other consumer functions is still far from reality.

Purchase SPIE Field Guide to Optical LithographyTraditionally, polymer or plastic is used as the substrate on which flexible electronics are built. There are several major challenges specific to these materials that make them unattractive from the perspective of performance and functionality. Their information processing speed is slow (the result of slow charge transport). They melt at low temperatures, which makes it difficult to subject them to traditional electronics processing. Moreover, their limited lithographic resolution makes creating small features on them a challenge. In large electronics, transfer printing can get around the low-resolution problem. But ultra-large-scale integration achieved via state-of-the-art deep UV lithography is not possible with smaller electronics, which require nanowire or nanoribbon transfer. While unconventional substrates like silicon-on-insulator (SOI), ultra-thin-body SOI, and silicon (111) do not have the same problems that polymer and plastic substrates do, they are expensive.

We have demonstrated a method of transforming traditional electronic circuits into flexible, transparent devices. This approach is cost-effective and does not sacrifice performance. We started with a bulk monocrystalline silicon (100) wafer, the most commonly used substrate in the electronics industry (see Figure 1). It has excellent electrical behavior: electron mobility is high in the silicon (100) plane. It is also as much as 50% less expensive than silicon (110), silicon (111), or SOI. The main challenge of our solution is the nature of the substrate. Silicon is rigid and brittle.


Figure 1. A generic process flow converts silicon electronics into flexible and transparent silicon fabric-based electronics. DRIE: Deep reactive ion etching. XeF2: Xenon difluoride. CMP: Chemical mechanical polishing.

We fabricated flexible devices using a typical process flow for silicon electronics. When designing the mask for patterning the devices on the silicon substrate, we made sure that the inactive areas were 20μm apart from each other and that each inactive area was at least 5μm wide: see Figure 1 (I). We covered the top with a layer of patterned photoresist. We then etched through the materials and the silicon substrate to isolate the devices through formation of 5μm-wide trenches, or channels: see Figure 1 (II).

We deposited an insulating dielectric thin film on the devices (furnace oxidation-based silicon oxide, plasma-enhanced chemical-vapor-deposition-based silicon oxide, or atomic-layer-deposition-based high-k dielectric, depending on the application). To form spacers to protect the trench walls, we removed the horizontal portion of the dielectric film using directional etching, while protecting the vertical portion of the film. We used an isotropic process to etch off the silicon vertically and laterally to create caves or scallops inside the silicon substrate, leaving a layer at least 25μm thick from the top of the substrate surface under the device areas: see Figure 1 (III). Our current process ensures a 10μm lateral etch on each side, resulting in a 20μm lateral etch (of the maximum width of the cave or scallop). This 20×20μm area is where the devices are located. We released and planarized the bottom substrate so that it could be reused.

We have applied our process to making metal-gate-stack-based metal-oxide-semiconductor capacitors with ultra-scaled effective oxide thickness and reduced gate leakage; high-k/metal-gate-stack-based metal-insulator-metal capacitors, the building blocks of memory devices for dynamic random access memory (DRAM); high-k/metal-gate-stack-based MOSFETs (metal-oxide-semiconductor field-effect transistors) to be used in static RAM; thermoelectric generators; movable microelectromechanical-systems-based actuators for displays and sensors; and, finally, microfabricated lithium-ion batteries for energy storage.9–13 We have successfully used our process on poly- and amorphous silicon, silicon oxide, and silicon germanium (see Figure 2).


Figure 2. Flexible and transparent silicon fabric being measured and displayed. (I) Electrical characterization while the flexible substrate is bent. (II) Bending curvature measurement. (III) A thermoelectric generator fabricated on flexible silicon wrapped around a wrist. (IV) A piece of flexible silicon placed on a torch with visible light below to show its semi-transparency.

The generic batch process is based on conventional micro-fabrication. This increases the mask count by one additional lithographic step, two thin-film-deposition processes, and three reactive ion-etch processes. These steps add to the cost. But in a CMOS foundry it is typical to use thousands of steps to fabricate integrated circuits with multilevel interconnects. In addition, our experience shows that we can obtain six layers of silicon fabric with devices by recycling a silicon substrate with an original thickness of 0.5mm.

Our method is advantageous because it is efficient in terms of time and materials. The throughput of the fabrication process is less than an hour. When two adjacent caves or scallops meet, they form a continuous chain of loosely attached top silicon fabric with devices: see Figure 1 (IV). Peeling off the top portion of the silicon requires no external support or additional processes. The fabric is transparent by virtue of the etch holes. Our calculation shows we only waste 16% of the area of the material. This is comparable to the loss in processing a normal integrated circuit, where shallow trench or mesa structures are used to ensure appropriate isolation among the devices.

One bottleneck of our process is that the scallops are elliptically or circularly shaped, which results in uneven silicon loss in the vertical direction. We have overcome this issue, and plan to document the results. Our trench-spacer-release process could expand the horizon of flexible electronics, while keeping them cost-effective.

Our next goal is to demonstrate the first fully flexible and transparent silicon-based programmable microprocessor. The most powerful, energy-efficient, and ultra-compact computer is the human brain. The folds in the cortex create a large surface area, which contains billions of neurons. We intend to apply the principle of this folded architecture in our future work on high-performance electronics.


Muhammad Hussain, Jhonathan P. Rojas, Galo A. Torres Sevilla
King Abdullah University of Science and Technology (KAUST)
Thuwal, Saudi Arabia

Muhammad Mustafa Hussain earned his PhD at the University of Texas, Austin. He has authored 147 research papers and holds 15 issued and pending US patents. He is an IEEE Electron Devices Society Distinguished Lecturer and a fellow at the Institute of Nanotechnology, UK.

Jhonathan Rojas is a PhD candidate at KAUST. His expertise is in process integration. His dissertation topic is self-powered electronics on flexible silicon.

Galo Torres Sevilla is a PhD candidate at KAUST. His research focuses on 1D nanoelectronics integration on flexible silicon.


References:
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8. K.-S. Chen, X. Zhang, S.-Y. Lin, Intrinsic stress generation and relaxation of plasma-enhanced chemical vapour deposited oxide during deposition and subsequent thermal cycling, Thin Solid Films 434, p. 190-202, 2003. doi:10.1016/S0040-6090(03)00462-0
9. J. P. Rojas, A. Syed, M. M. Hussain, Mechanically flexible, optically transparent porous mono-crystalline silicon substrate, IEEE 25th Int'l Conf. MEMS, p. 281-284, 2012. doi:10.1109/MEMSYS.2012.6170146
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11. H. M. Fahad, M. M. Hussain, High performance silicon nanotube tunnelling FET for ultra-low power logic applications, IEEE Trans. Elect. Dev. 60, p. 1034-1039, 2013. doi:10.1109/TED.2013.2243151
12. J. P. Rojas, G. T. Sevilla, M. M. Hussain, Structural and electrical characteristics of high-k/metal gate MOSCAPs fabricated on flexible, semi-transparent silicon (100) fabric, Appl. Phys. Lett. 102, p. 064102, 2013. doi:10.1063/1.4791693
13. G. T. Sevilla, J. P. Rojas, S. Ahmed, A. Hussain, S. B. Inayat, M. M. Hussain, Silicon fabric for multi-functional applications, 17th Int'l Conf. Solid-State Sensors, 2013.