Spintronic devices use properties of magnetic material components and/or carrier spin, and have found success in low-power, high-performance nonvolatile magnetic random access memories (MRAMs). But they lack gain and other characteristics required for broader information processing. CMOS field effect transistors (FETs) have output levels larger than their input levels (voltage and power gain), so that each device is capable of providing adequate input for several subsequent devices. This ‘fanout’ enables operation of chains of devices in a circuit or array of gates, a capability critical to the broad processing applications where CMOS succeeds but draws high power. It would be ideal if we could combine the low power attribute of spintronics with the fanout capability of semiconductor logic.
At present, the dominant spintronic device is the magnetic tunnel junction (MTJ).1The MTJ is a sandwich of two thin ferromagnetic metal films separated by a very thin tunnel barrier, and has two different resistance states that depend on the magnetization states (spin states) of the ferromagnetic layers. Attempts to make semiconductor spintronic devices have had some success, but their characteristics fall far short of the MTJ. Similarly, attempts to use magnetic structures for logic have not been viable in semiconductor-based integrated circuits.2We have developed a magnetic-field-controlled diode as a semiconductor magnetoelectronic device. In addition, we have made circuits of a few diodes to demonstrate dynamically reconfigurable Boolean logic, an approach to reprogrammable logic that offers new capabilities.3
Figure 1. (a) An indium antimonide, InSb, p-n bilayer avalanche diode, with (b) schematic description of transport in a magnetic field, B, and (c) the resulting current-voltage, I-V, curves. B⊙: Magnetic field applied along z-axis. B⊗: Magnetic field applied along negative z-axis. V⊙: Characteristic voltage, above which current rises exponentially, for applied magnetic field B⊙. V⊗: Higher characteristic voltage, above which current rises exponentially, for applied magnetic field B⊗.
Doping a semiconductor with a small number of donor impurities improves the conductivity dramatically. For negative donors (n-type) the carriers are electrons, and for positive donors (p-type) the carriers are holes. The interface between a p-n bilayer is characterized by interdiffusion of both kinds of carriers and strong internal electric fields. A bias voltage applied across such a p-n diode produces a highly nonlinear effect. A small bias yields a small current, but above a characteristic voltage the current increases exponentially. The resulting current-voltage (I-V) curve is known as a diode characteristic. An avalanche diode is typically made of a simple n-type channel and operates in a different way, but the result is a similar diode characteristic. In an avalanche diode, the electric field from the bias voltage accelerates each electron until it scatters. Each scattering event emits phonons that diminish the kinetic energy, but after a few of these ‘ballistic trajectories’ the electron has sufficient energy to scatter with impact ionization, thereby creating new carriers. Carrier generation increases with increasing voltage, resulting in a nonlinear I-V characteristic. There is a high-current state with large conductance (dI/dV), a low-current state with small dI/dV, and the characteristic threshold voltage, Vt, lies between.
Figure 2. (a) A circuit of two identical devices, NP1 and NP2, has magnetic-field-dependent output that corresponds to (b) an AND gate for Vtotal=22 .05V or (c) an OR gate for Vtotal=22 .20V.
The key innovation in our modified avalanche diode is the use of a p-n bilayer for the channel. An ‘NP’ sample has a 0.2μm-thick n-type indium antimonide (InSb) top layer and a 6μm-thick p-type InSb bottom layer: see Figure 1(a). In zero magnetic field (B=0), the n-layer has higher mobility and lower resistivity, carries most of the current, and behaves like a typical avalanche diode. For a magnetic field applied along the direction of the z-axis, coming up out of the paper (B⊙), electrons are deflected up into curved trajectories by the Lorentz force: see Figure 1(b). Higher voltage is needed to reach the high current state. The characteristic voltage, above which current rises exponentially, Vt, is shifted higher: see Figure 1(c), where Vt is denoted V⊙. For a magnetic field applied along the direction of the negative z-axis (B⊗), trajectories are deflected down: see Figure 1(b). Now the trajectories terminate at the p–n interface where recombination with holes occurs. Carrier lifetimes are shortened, and Vt is shifted to an even higher voltage (V⊗): see Figure 1(c).
Figure 3. (a) A circuit of three devices, NP5, NP6, and PN2, uses the magnetic configuration of PN2 to select the Boolean function, as confirmed by (b) the experimental truth table. The total bias voltage Vtotalremains the same, but V12—the voltage drop across the two devices NP5 and NP6—varies between two values that depend on the magnetic state of PN2.
The I-V traces in Figure 1(c) show the basis for digital electronic applications. The threshold voltages, V⊙ and V⊗, are different for the two magnetic states. At a chosen voltage (11.0V), the device has two distinct states that are selected by B. As a switch, our device's characteristics are very good. The ratio of high to low current is about 5. The conductance (dI/dV) ratio in the high-current state to that in the low state is a factor of ∼100.
A circuit of two identical devices, NP1 and NP2, demonstrates operation as a reconfigurable AND/OR logic gate: see Figure 2(a). The current, I, is the same for both devices and has the high-state value only if V1 and V2 exceed the threshold voltages for each device, V1 > Vt1 and V2 > Vt2, where Vt1 and Vt2 can have values V⊙ or V⊗. In any other case, I has the low-state value. The circuit performs as an AND or OR gate depending on bias value Vtotal. The Ioutput axis represents circuit current, and bar plots for four different input configurations are presented. Vertical bars represent voltage drops across each of the two devices, red (blue) corresponding to a device in the presence of positive (negative) field. In the first configuration of Figure 2(b), NP1 and NP2 are both in negative field (inputs binary 0 and 0), V1 and V2 are both less than Vt = V⊗, and the current is low. Only in the fourth configuration where NP1 and NP2 are in positive field with binary inputs 1 and 1, and both V1 and V2 are larger than Vt = V⊙, does the circuit have high current. The input/output characteristics match the AND gate truth table. The OR gate operates with a similar description: see Figure 2(c).3
Our room-temperature experiments were performed using a magnetic field applied to individual devices in the circuit. For applications, a fully integrated cell is required and can be realized by fabricating ferromagnetic structures in proximity with the diode channels and using their fringe magnetic fields as the diode inputs.3 The field orientation can be reversed by switching the ferromagnet magnetization using a spin-torque-transfer current pulse.4 Circuits of these integrated cells would operate at constant voltage, using a magnetic field to select the Boolean operation. Magnetic-field-controlled operation, using our prototypes and external fields, is shown in Figure 3. Bias Vtotal is constant, but the voltage drop V12 across the input devices varies between two values that depend on the magnetic state of the function selector PN2: see Figure 3(a). This results in the truth table in Figure 3(b).
The circuit in Figure 3 demonstrates nonvolatile reconfigurable logic. The state of the cell, and therefore the output, is stored with zero quiescent power. The circuit dissipates power during an operation, but no power whenever it is inactive. The quiescent power of CMOS logic is high, and an approach that reduces average power could be important for many applications. The prospects for scaling are good, and the output current of a scaled device should be adequate for writing the input state of a subsequent device, offering current gain, and enabling fanout. Our ongoing research is focused on the fabrication of small devices (on the order of one micron) to test scaling. We are also fabricating integrated cells that include patterned ferromagnetic structures that will supply magnetic field inputs.
Mark Johnson gratefully acknowledges the support of the Office of Naval Research. Jinki Hong, Jindong Song, and Joonyeon Chang acknowledge the support of the Korean Institute of Science and Technology (KIST). This work was performed at KIST, Seoul, Republic of Korea.
Naval Research Laboratory
Laboratory of Display and Semiconductor Physics
Republic of Korea
Jin Dong Song, Joonyeon Chang
Korean Institute of Science and Technology (KIST)
Seoul, Republic of Korea
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