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Journal of Micro/Nanolithography, MEMS, and MOEMS Special Section Calls for Papers

To submit a manscript for consideration in a Special Section, please prepare the manuscript according to the journal guidelines and use the Online Submission SystemLeaving site. A cover letter indicating that the submission is intended for this special section should be included with the paper. Papers will be peer‐reviewed in accordance with the journal's established policies and procedures. Authors who pay the voluntary page charges will receive the benefit of open access.

View the list of special sections that have already been published on the SPIE Digital Library.

Calls for Papers:

Extending VLSI and Alternative Technology with Optical and Complementary Lithography

Control of IC Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension

Photomask Manufacturing Technology

April-June 2016

Extending VLSI and Alternative Technology with Optical and Complementary Lithography

Guest Editors:

Kafai Lai
IBM Semiconductor R&D Center
2070 Route 52
Hopewell Junction, New York 12533
E-mail: kafailai@us.ibm.com

Andreas Erdmann
Fraunhofer Institute for Integrated Systems and Device Technology
Schottkystr. 10
Erlangen 91058, Germany
E-mail: andreas.erdmann@iisb.fraunhofer.de

Call for Papers: While extreme ultraviolet (EUV) lithography is still maturing, optical lithography is expected to continue as the primary lithographic technology for manufacturing over the next several years. Extension of water-based immersion lithography to below 20-nm half-pitch (10-nm logic node) requires the use of innovative resolution enhancement techniques, solutions to complexities introduced by hyper-NA optics, and extensive use of double- or multiple-sequential exposure and patterning techniques, and even complementary use of optical lithography with nontraditional techniques. In addition to resolution, very tight process (and overlay) control and high-quality photomasks are also necessary. The successful use of optics to provide viable working solutions for these device nodes will require fundamental integration of all aspects of the patterning process. The cost of advanced lithography is another concern that is in need of creative solutions, such as "freezing" the first resist in a double patterning approach, and the use of directed self-assembly in optically created guiding patterns. For the 14-nm node and beyond, early design technology co-optimization is necessary to ensure the patterning solution can enable design for products. This special section welcomes paper submissions covering topics that are advancing the field of optical nano- and microlithography that extend optical lithography beyond the 14-nm technology node and enable circuit scaling.

In addition to scaling in the horizontal direction, vertical scaling is becoming a way to maintain Moore's law of device scaling through the use of advanced imaging and overlay techniques for 3-D wafer integration. Furthermore "More than Moore" scaling for non-very large-scale integration (VLSI) applications is gaining much momentum in industry application and academic research. Novel techniques like 3-D imaging/printing, as well as optical microsculpturing recently provided versatile applications beyond the electronics industry. Papers on such patterning topics using optics are welcome as well.

Besides traditional semiconductor manufacturing, there is also an increasing number of applications for optical lithography in other fields of micro- and nanotechnology. The majority of these applications are not driven by resolution or minimum feature sizes, but by diverse technology elements and cost-of-ownership requirements. The adaptation of existing deep utlraviolet (DUV) projection systems and the further development of alternative optical lithographic require innovative solutions.

Suggested topics for this special section include, but are not limited to, the following:

Pushing the limits of 193-nm optical lithography

  • Innovative optical methods to break diffraction limit
  • Holistic integration for lithography at k1 < 0.3
  • Layout optimization to extend the limits of optical lithography
  • Design compliance towards new patterning solutions
  • Mask technology advances: process complexity, mask fidelity characterization, defects detection, and repair 
  • Hyper-NA imaging with mask topography, Jones pupils, and 3-D photoresist effects 
  • 193-nm light sources: laser bandwidth, source fidelity, apodization, and other effects
  • Implementation and integration of resolution enhancement methods

Complementary lithography

  • Enhancement of optical lithography by emerging new material and processing techniques: directed self assembly, two-photon absorption materials, optical metamaterials
  • Combination of different exposure techniques, including projection, multiple-beam interference, and holographic lithography
  • Combination of exposures at different wavelengths or with electrons
  • General design, processing, and metrology challenges

Advanced computational lithography

  • Advanced mask decomposition for multiple patterning
  • Advanced pattern correction and verification
  • Rigorous and compact modeling of optical and process effects
  • Advanced compact model verification and calibration techniques
  • Source, mask, pupil, and target co-optimization
  • High-performance computing environment for computational lithography
  • Advanced pattern selection and matching methods
  • Mask writing shot counts minimization for advanced resolution-enhancement technology

Design technology co-optimization

  • Advanced ground rules methodologies
  • Innovative design flow for multiple patterning and nontraditional patterning techniques
  • Systematic discussion of process-induced design restriction's impacts to design
  • Unidirectional designs with cut masks to reduce patterning complexity
  • Advanced retargeting of designs

Multiple patterning process integration

  • Multiple exposure and double masking techniques, including requirements and challenges of cut-mask 
  • Multiple patterning process integration issues such as etch and thin-film deposition
  • Advanced mask type optimization
  • Advanced processing steps including negative tone development process, resist freezing, etc.

Pushing lithography tools and subsystems

  • Innovative subsystems to push for nanometer-scale alignment and overlay
  • Process optimization for improving product overlay
  • Advanced monitoring and optimization algorithms to minimize CD variation
  • Innovative scanner optics design and manufacturing
  • Advanced in-situ metrology for tools control
  • High-performance excimer laser sources

Optical lithography for applications beyond standard semiconductor fabrication

  • New applications including Si-photonics, MEMS, sensors, solar energy harvesting, and display and lighting technology
  • Involved special challenges and solutions: non-Manhattan layouts, thick photoresists, large pattern areas, excellent control of CD uniformity and 3-D profile shapes
  • Adaptation of established techniques including deep ultraviolet projection, mask aligners, laser direct write
  • New techniques including stimulated emission depletion (STED)-inspired techniques, interference lithography, Talbot and holographic lithography, near-field lithography
  • Design, modeling, and metrology solutions for new applications.

Closed for submissions.


April-June 2016

Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension

Guest Editor:

Alexander Starikov
I & I Consulting
2215 Greer Road
Palo Alto, California 94303-3129
E-mail: alstarikov@gmail.com

Call for Papers: Control of device dimensions in patterning is conventionally defined as consisting of two complementary components assumed to be independent: size [critical dimension (CD)] and placement [from mask registration and wafer alignment to layer-to-layer centerline overlay (OL)]. Two kinds of dimensional metrology are practiced, in dissimilar application environments and typically on different tools, with process control and systematic corrections applied in two separate control loops.

Lithography extensions through pitch multiplication and directed self-assembly lead to an intermixing of CD and OL. Unlike in conventional lithography, where physical mechanisms driving size variations are different from those in placement errors allowing for separate metrology and control, there is a strong need to self-consistently measure and control both CD and OL. New approaches to IC patterning and unprecedented expectations of device OL drive demand for metrology and control of image placement.

This special section of the Journal of Micro/Nanolithography, MEMS, and MOEMS seeks to offer comprehensive technology overviews of image placements, in-depth accounts of the latest technology and metrology equipment, image placement variation and metrology error modeling, novel applications, methods for control of image placement, and, ultimately, methods for control of device CD and OL.

Please submit a technology overview, a consolidation of earlier work, or an original technical paper related to metrology and control of image placement and device overlay in IC manufacture. Topics of interest include, but are not limited to, the following:

Alignment, registration, and overlay metrology

  • Metrology of centerline and the associated performance-limiting issues
  • Measurement self-consistency, matching, accuracy, cross-technology comparisons
  • Tool-related error mechanisms, their control and reduction, performance metrics
  • Metrology design process integration, metrology quality and performance metrics
  • Ultimate performance of metrology of image placement, hybrid metrology

Methods, technologies, and applications for control of device overlay

  • Device yield/performance and e-test versus in-line measurement of CD and OL
  • Sources of device size and placement variations, their signatures in space and time
  • Segmentation of device variance and control of its principal components
  • Modeling, prediction, and control of systematic variations, and of residual components
  • Design, metrology, and process integration for efficient high-volume manufacturing.

Closed for submissions.


April-June 2016

Photomask Manufacturing Technology

Guest Editors:

Masato Shibuya
Tokyo Polytechnic University
Media and Image Technology Department
1583 Iiyama
Atsugi-Shi, Kanagawa, Japan
E-mail: shibuya@photo.t-kougei.ac.jp

Morihisa Hoga
Dai Nippon Printing Co., Ltd.
Research and Development Center
250-1 Wakashiba
Kashiwa, Chiba, Japan
E-mail: Houga-M@mail.dnp.co.jp

Kiwamu Takehisa
Lasertec Corporation
2-10-1 Shin-yokohama, Kohoku-ku
Yokohama, Kanagawa
222-8552 Japan
E-mail: kiwamu.takehisa@lasertec.co.jp

Call for Papers: Photomasks are a critical part of almost all lithography processes. In integrated circuit manufacturing, the quality of the final device can be limited by the quality of the photomasks used to fabricate them. Additionally, many advances in lithographic capabilities are enabled by novel photomask approaches.

Critical parameters for photomask fabrication include resolution, defectivity, mask inspection and repair, critical dimension control, overlay, and throughput (write time). To address these key parameters and encourage the development of new technologies, we invite the submission of technical papers that will improve the design, fabrication, and use of photomasks for lithography:

  • Materials of and for photomasks
  • Fabrication process steps and equipment for photomasks (process and equipment for developing, etching, cleaning etc.)
  • Photomask writing tools and technologies
  • Mask metrology tools and technologies
  • Mask inspection tools and technologies
  • Mask defect repair tools and technologies
  • Photomasks with resolution enhancement technologies: phase-shifting mask (PSM), optical proximity correction (OPC), source mask optimization (SMO), and multiple patterning
  • Technologies and infrastructures for extreme ultraviolet lithography (EUVL) masks
  • Nanoimprint lithography and templates for semiconductors
  • Mask data preparation
  • Photomasks for non-semiconductor applications.

Closed for submissions.


Published Special Sections:

On the Interface of Holography and MEMS (October-December 2015)
Guest Editors: Partha Banerjee, Pierre-Alexandre Blanche, Christophe Moser, and Myung K. Kim

Alternative Lithographic Technologies IV (July-September 2015)
Guest Editors: Douglas J. Resnick, Ricardo Ruiz, and Hans Loeschner

Control of Integrated Circuit Patterning Variance Part 1: Metrology, Process Monitoring, and Control of Critical Dimension (April-June 2015)
Guest Editors: Alexander Starikov and Matthew Sendelbach

Continuation of Scaling with Optical and Complementary Lithography (January-March 2015)
Guest Editors: Kafai Lai and Andreas Erdmann

Holistic/Hybrid Metrology (October-December 2014)
Guest Editors: Alok Vaid and Eric Solecky

Alternative Lithographic Technologies III (July-September 2014)
Guest Editors: Douglas J. Resnick, Christopher Bencher, and Ricardo Ruiz

Metrology and Inspection for 3-D Integrated Circuits and Interconnects (January-March 2014)
Guest Editors: Yi-sha Ku and Alexander Starikov

Emerging MOEMS Technology and Applications (January-March 2014)
Guest Editors: M. Edward Motamedi, Joel Kubby, Patrick Ian Oden, and Wibool Piyawattanametha

Optical Lithography Extension Beyond the 14-nm Node (January-March 2014)
Guest Editors: Will Conley and Kafai Lai

Advanced Fabrication of MEMS and Photonic Devices (October-December 2013)
Guest Editors: Georg von Freymann, Mary Ann Maher, and Thomas J. Suleski

Advanced Plasma-Etch Technology (October-December 2013)
Guest Editors: Ying Zhang, Qinghuang Lin, and Gottlieb S. Oehrlein

Alternative Lithographic Technologies (July-September 2013)
Guest Editors: Will Tong and Douglas J. Resnick

Photomasks for EUV Lithography (April-June 2013)
Guest Editors: Christopher J. Progler and Frank E. Abboud

Alternative Lithographic Technologies (July-September 2012)
Guest Editors: William M. Tong, Douglas J. Resnick, and Benjamin Rathsack

Directed Self-Assembly (July-September 2012)
Guest Editors: Daniel P. Sanders and William H. Arnold

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS III (April-June 2012)
Guest Editors: Sonia M. García-Blanco and Rajeshuni Ramesham

EUV Sources for Lithography (April-June 2012)
Guest Editors: Vivek BAkshi and Anthony Yen

Dimensional Metrology with Atomic Force Microscopy: Instruments and Applications (January-March 2012)
Guest Editors: Ronald Dixson and Ndubuisi G. Orji

Theory and Practice of MEMS, NEMS, and MOEMS (January-March 2011)
Guest Editor: Yu-Cheng Lin

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS II (October-December 2011)
Guest Editor: Rajeshuni Ramesham

Line-Edge Roughness (October-December 2011)
Guest Editors: Chris A. Mack and Will Conley

Metrology (October-December 2011)
Guest Editors: Moshe Preil and Shaunee Cheng

BioMEMS, Theory and Practice of MEMS/NEMS, and Sensors (July-September 2010)
Guest Editor: Yu-Cheng Lin

Extreme-Ultraviolet Lithography (October-December 2009)
Guest Editors: Kevin Cummings and Kazuaki Suzuki

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS (July-September 2009)
Guest Editors: Rajeshuni Ramesham and Allyson L. Hartzell

Computational Lithography (July-September 2009)
Guest Editors: Donis Flagello and Chris Mack

Theory and Practice of MEMS/NEMS/MOEMS, RF MEMS, and BioMEMS (April-June 2009)
Guest Editor: Yu-Cheng Lin

Extreme-Ultraviolet Interference Lithography (April-June 2009)
Guest Editor: Franco Cerrina

Double-Patterning Lithography (January-March 2009)
Guest Editor: William H. Arnold

Silicon-Based MOEMS and Their Applications (April-June 2008)
Guest Editors: Harald Schenk and Wibool Piyawattanametha

Resolution Enhancement Techniques and Design for Manufacturability (July-September 2007)
Guest Editor: Alfred K. K. Wong

Bio-MEMS and Microfluidics (April-June 2006)
Guest Editors: Wanjun Wang and Ian Papautsky

Nanopatterning (January-March 2006)
Guest Editors: Kees Eijkel, Jill Hruby, Glen Kubiak, M. Scott, Volker Saile, and Steven Walsh

MOEMS Design, Technology, and Applications (October-December 2005)
Guest Editor: M. Edward Motamedi

Polarization and Hyper-NA Lithography (July-September 2005)
Guest Editor: Donis Flagello and Christopher J. Progler

Next Generation Lithography (January-March 2005)
Guest Editor: Walt Trybula

Mask Technology for Optical Lithography (April-June 2004)
Guest Editor: Kevin D. Cummings and Frank M. Schellenberg

Immersion Lithography (January-March 2004)
Guest Editor: William H. Arnold

Surface Micromachining (October-December 2003)
Guest Editors: Jeffry J. Sniegowski and James H. Smith

Micro-Optics for Photonic Networks (October-December 2003)
Guest Editor: Thomas J. Suleski

Lithography for Sub-100-nm Device Fabrication (October-December 2002)
Guest Editor: William H. Arnold

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