SPIE Membership Get updates from SPIE Newsroom
  • Newsroom Home
  • Astronomy
  • Biomedical Optics & Medical Imaging
  • Defense & Security
  • Electronic Imaging & Signal Processing
  • Illumination & Displays
  • Lasers & Sources
  • Micro/Nano Lithography
  • Nanotechnology
  • Optical Design & Engineering
  • Optoelectronics & Communications
  • Remote Sensing
  • Sensing & Measurement
  • Solar & Alternative Energy
  • Sign up for Newsroom E-Alerts
  • Information for:
SPIE Photonics West 2018 | Call for Papers

SPIE Defense + Commercial Sensing 2018 | Call for Papers




Print PageEmail PageView PDF

Micro/Nano Lithography

The View from Above

Aerial-image-based photomask inspection minimizes false positives.

From oemagazine February 2004
31 February 2004, SPIE Newsroom. DOI: 10.1117/2.5200402.0004

Photolithographic masks are the stencils used to replicate the integrated circuit patterns of VLSI devices on silicon wafers. While standard masks consist of a patterned chrome film over a quartz substrate, current practice includes phase masks produced with MoSi or etched quartz. The desired pattern is transferred to the semiconductor film by projecting the mask image at a 4:1 reduction onto a photosensitive resist coating with a step-and-scan lithography tool (stepper), developing the resist, and processing the film through the resultant pattern.

A single mask can be used in the production of hundreds or even thousands of wafers. A wafer can contain tens to hundreds of dies, each of which is processed to become a fully functional device; therefore an undetected error or defect in the mask can cause tremendous yield loss. To minimize this loss, all masks, or reticles, are inspected for quality control several times during their manufacturing process.

Currently, manufacturers typically use one of three inspection methods: die-to-database inspection, in which the mask image is compared to the design data; die-to-die inspection, in which the images of nominally identical dies within a mask are compared to each other; and contamination inspection, in which the mask is checked for non-pattern-related defects, e.g. particles. When defects are found, the mask is repaired (if possible) and re-inspected. Conventional mask inspection systems use short wavelengths and high-magnification optics to detect defects down to 100 nm in size.

The basic problem with current solutions in mask defect detection is the discrepancy between those defects found by the inspection systems and those of interest to the user. Advanced reticles build on physical optical effects to enhance image quality and reduce printable feature size. Inspection systems that do not illuminate the reticle at the stepper wavelength and do not reproduce the physics of the optical path cannot account for these effects in the course of inspection, either detecting mask defects that do not print or missing defects that can compromise the printed devices. To address this issue, our group at Applied Materials (Rehovot, Israel) has developed a new technology for mask inspection—aerial-image-based mask inspection.1

New Challenges

As the design rules shrink, designers must turn to subwavelength lithography—printing features as small as 65 nm with 193-nm illumination, working below the diffraction limit, wherein the optics cannot faithfully reproduce the desired pattern without recourse to resolution enhancement techniques (RETs). RETs include optical proximity correction (OPC), in which subwavelength, non-printing additions such as serifs sharpen up corners and line-ends, and alternating phase-shifting masks (PSM), in which the light from adjacent features undergoes phase inversion to increase contrast and enhance resolution. Manufacturing high-quality RET masks becomes increasingly difficult as the feature sizes shrink and the manufacturing technologies become more complex, making masks one of the primary challenges at the 65-nm node.

The actual printability of subwavelength defects is a complex issue: some may not print at all, having no effect on yield, while others may produce large pattern errors, effectively killing the device. The relative dimensional scaling between a mask defect and the printed defect, called mask-error enhancement factor (MEEF), is given by:

where the factor of four accounts for the nominal 4:1 stepper reduction ratio and ΔCD refers to the change in critical dimension (CD), e.g., the width of a line or the diameter of a contact. As illustrated below, the MEEF depends on the pattern features, geometry, and density. In high MEEF patterns (MEEF greater than one), a small defect on the critical features of the reticle is enlarged when transferred to the wafer. Conventional inspection tools examine the mask pattern itself and so cannot predict how a defect will turn out on the wafer; detecting and classifying defects in high-MEEF masks presents challenges, and the results may be misleading.

Defect classification methodologies include hardware (for example, the aerial-imaging microscopes used for final qualification of reticles after repair) and software (for example, simulations of the expected aerial image, based on a reticle image). Both of these methods incorporate traditional inspection hardware that scrutinizes the reticle, not the image it produces. Improving yield requires an alternative solution to mask inspection.

Aerial Imaging vs. Mask Imaging

Many reticle defects such as extrusions, protrusions, and proximity pinholes and pindots manifest themselves on the wafer as CD variations and contribute to CD non-uniformity. The geometry of the pattern changes between mask and wafer, though, because of the imaging optics of the stepper. What we see on the mask is not necessarily what we will see on the wafer. Consider a bump defect between two lines in an alternating PSM. On the wafer, this defect produces a CD variation in the lines but the bump itself is not printed at all. Similarly, a clear protrusion from the corner of a contact hole will cause a CD variation on the wafer as well as shape asymmetry in the contact hole, but the defect itself will not be resolved or printed.

Figure 1. For this pattern of sparse 70-nm lines on an alternating (phase-etched) phase shift mask (MEEF<1), the size of defect on the mask (top), directly affects the magnitude of the as-printed defects on the wafer (bottom) (the wafer images are mirrored relative to the reticle images). The 120-nm defect does not cause an adverse CD variation, and the 162-nm defect is on the borderline of printing, while the 210-nm defect is critical to device functionality. Courtesy INTERNATIONAL SEMATECH.

Many of the defects detected by traditional inspection methods are not transferred to the wafer, do not affect the CD uniformity of the wafer, and are of little interest to semiconductor manufacturers. The effect of a defect is, not surprisingly, related to size (see figure 1). In the sparse pattern shown in the figure, a 120-nm defect does not affect CD adversely, whereas a defect nearly twice that size directly impacts device functionality.

The aerial image of a mask consists of the light intensity distribution at the wafer plane, as produced by the stepper illumination source and projection optics. While the aerial image does not predict the final pattern in the developed photoresist, it does faithfully reproduce all the optical physics including the effects of RETs and the nonlinear response of defect transfer described by MEEF. An inspection technology based on aerial imaging can thus alert the operator to defects that actually print, allowing them to ignore those that may be present on the mask but have no impact on the final result.

Figure 2. Aerial inspection uses a pulsed excimer laser at the stepper wavelength. The optics are designed to emulate the stepper optical path, including varying the illumination and projection NA. Unlike stepper optics, the inspection optics enlarge the reticle image onto a CCD camera.

An aerial image inspection tool should be designed to reproduce the physical effects of the stepper optics, while examining at a small area of the reticle with high magnification to enable defect detection. The aerial imaging inspection system we propose uses a light source and illumination optics similar to those used for a lithographic stepper (see figure 2). The illumination used is a pulsed excimer laser operating at lithographic wavelength. The imaging optics for the inspection system are designed to emulate the stepper optics; the numerical aperture (NA) and illumination settings (sigma values) of the stepper can be set on the inspection tool, and various off-axis illumination schemes (e.g., annular, quadrupole) can be applied. Instead of imaging the pattern onto a wafer, however, the system images the pattern onto a CCD camera. Processing the resultant image provides an accurate assessment of mask performance and defects.

The inspection concept is a classical die-to-die inspection model in which the identical dies of a reticle are compared one to the other to reveal defects. Since the inspection is at-wavelength and uses aerial imaging, issues such as OPC, MEEF, and phase effects are inherently accounted for. Using this method, mask makers could inspect and qualify the reticle in a single step.

The defect location in the aerial image is identical to the defect location in the mask and the mapping is very straightforward. To assist the user in identifying defect cause and in choosing repair strategy, the system is also equipped with additional optics for review, which provide a high-NA, highly magnified optical image of the defect.

Detecting Defects

Figure 3. The optical image of an edge-intrusion defect (top left) captures different data than the aerial image of the same defect (top right). The data plots (bottom) show vertical cross sections of the defect area with the defect (red) and without the defect (blue). The direct-inspection data yields an estimated CD variation of 12%, whereas the aerial image data yields an estimated CD variation of 33%, implying a MEEF of ~2.75. Courtesy AMAT.

A comparison of the MEEF calculation for the reticle image and the aerial image of an attenuated PSM with a contact defect shows the enhanced performance of the aerial image method (see figure 3). The defect consists of a dark intrusion at the lower edge of a contact. We estimated the CD variation from image cross sections, measuring a 33% CD variation in the aerial image versus a 12% CD variation in the reticle image; this data implied a MEEF factor of 2.75. The actual CD variation on the wafer printed from this reticle was 35%, consistent with the aerial image measurement.

These examples, as well as the example of non-printing errors shown in figure 1, clearly illustrate how the defect in the aerial image is much more representative of the transferred pattern than the image of the defect on the reticle. The aerial image of the mask provides more useful information on the quality of the mask, compared to the magnified mask image.

High-quality masks for 193-nm photolithography, manufactured using resolution enhancement techniques such as OPC and phase shift, are among the enabling technologies for next-generation chips. Effective inspection of these masks is increasingly difficult; as mask complexity grows, feature sizes shrink and defect printability is no longer directly correlated. An aerial-image-based mask inspection tool designed to solve these issues should reproduce the physical effects of the stepper optics, imaging the reticle with high magnification to enable detection of small defects. oe

X Marks the Spot

Introduced in 2001, X architecture is an on-chip interconnect architecture based on the pervasive use of diagonal wiring. Compared to the conventional rectilinear (Manhattan) architecture, the approach reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power consumption, and cost. One major practical question remained to be answered, though: Would implementing massive numbers of diagonal wires introduce unforeseen issues for photomasks?

Several members of the X Initiative industry consortium collaborated to answer this question for the 130-nm process node. The experiment involved applying optical proximity correction (OPC) to the metal layers four and five of an X-architecture design. The results demonstrated that data sizes and runtimes were well within the range of normal, as compared to a Manhattan design.

DuPont Photomasks (Round Rock, TX) created test photomasks using GDS data supplied by Cadence Design Systems Inc. (San Jose, CA) with added OPC features. Data was fractured using CATS software from Synopsys (Mountain View, CA). Due to the large number of diagonal figures, the team wrote the mask pattern with a laserbased mask pattern generation system (ALTA 4000; Etec Systems; Santa Clara, CA), using a high-throughput raster-laser scan-in approach. Printing required 113 minutes. There were no data prep issues and lithography data file sizes for both layers were reasonable.

The 130-nm mask was inspected using a TeraStar reticle inspection system from KLA-Tencor (Milpitas, CA), which was able to handle the diagonal structures of X-architecture designs. Of particular interest was the question of whether the advanced OPC would introduce any inspection problems; in general, the use of OPC will often result in greater data preparation times and larger data preparation files.

Inspection results from X-architecture photomask show single contamination defect; no false defects flagged.

The process involved 69 s of data preparation time and produced a data volume of 11.7 MB, comparable to those associated with traditional IC layout design. The system detected a few defects that had no lithographic significance, and the false-defect counts for diagonal features was comparable to the conventional Manhattan architecture.

The experiment demonstrated that X-architecture masks for the 130-nm node can be manufactured successfully using existing photomask preparation, writing, and inspection tools with write-times and quality comparable to those for Manhattan designs. Perhaps even more important, this effort provides an example of how collaboration among members of the design chain can help overcome technical obstacles to the introduction of new design and/or manufacturing techniques. As the semiconductor industry pushes ever further into the subwavelength world, this kind of collaboration will become more and more necessary to keep on track with Moore's Law.

Aki Fujimura
Aki Fujimura is chief technology officer of Cadence Design Systems Inc., San Jose, CA.


The authors would like to thank Sematech and Taiwan Semiconductor Manufacturing Company Ltd. for providing mask and wafer CD images used in this article.


1. Shirley Hemar, Anja Rosenbusch, et al., Proc. SPIE 5038, p. 929-934 (2003).

Shirley Hemar, Anja Rosenbusch, Reuven Falah
Shirley Hemar is a product marketing engineer, Anja Rosenbusch is KPU head, and Reuven Falah is a member of the technical marketing staff in the Mask Inspection Group of the Process Diagnostics and Control Unit of Applied Materials, Rehovot, Israel.