Joseph Sawiki: Design for test provides valuable feedback
The simple approach to lithography has given way to more complicated solutions driven by the proliferation of complex patterns. For those who work in electronic design automation, this means they must now put in place systems capable of simulating increasingly diverse sets of geometries. To improve manufacturability, many fabs have adopted restricted design rules limiting the number and types of geometries designers can use.
Looking ahead, design and verification tools should continue to blend evolutionary trends such as enhancements to three-dimensional mask design and yield learning with more revolutionary changes such as limiting geometries and pattern options available to designers.
Joseph Sawicki is the Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics Corp. An expert in IC nanometer design and manufacturing challenges, Sawicki is responsible for Mentor's design-to- silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line. Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.