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Micro/Nano Lithography

Researchers Work to Extend Semiconductor Metrology to Features of 40 nm and Below

Eye on Technology - SMALL MEASURES

From oemagazine May 2005
30 May 2005, SPIE Newsroom. DOI: 10.1117/2.5200505.0001

In this false-color image, the large purple rectangle is a chip feature about 40 X 150 nm. The magnified section shows the planes of silicon atoms used to calibrate the measurement.

The features on integrated circuits are getting ever smaller, but exactly how big they are is hard to say. As feature sizes shrink below 100 nm, they have passed the ability of current metrology methods to measure them accurately. "The requirements for metrology as outlined in the roadmap are not being met," says Vladimir Mancevski, chief technology officer of Xidex Corp. (Austin, TX), a developer of carbon nanotube technology. Indeed, the 2004 edition of the International Technology Roadmap for Semiconductors shows a wide swath of red, meaning "manufacturable solutions are not known" for current and future metrology needs.

Several groups are tackling the next-generation metrology problem. Xidex, working with the University of Texas at Austin and the semiconductor manufacturers' consortium SEMATECH (Austin, TX), recently showed that carbon nanotubes can act as the tips of atomic force microscopes (AFM) to scan the surfaces of computer chips for high- resolution metrology. The work is under the auspices of the Advanced Materials Research Center, a cooperative effort between SEMATECH and the state of Texas.

The team started with a conventional silicon tip and, through electro-deposition, placed a catalyst like nickel or cobalt in holes in the tip. They then placed the tip in a chemical vapor deposition chamber and grew the nanotubes. Because they made the holes parallel to each other and made sure the catalyst sat in the holes and nowhere else, they were able to get a fixed array of carbon nanotubes, instead of the clusters that other processes produce.

The multiwalled carbon nanotubes, essentially concentric cylinders of nanotubes, have diameters of around 10 nm and lengths of a few microns. That means they can fit into the deep trenches and small holes in chip designs where standard silicon-tipped AFM probes cannot. They also last much longer. They would have to be changed once a month, as opposed to once a day for a silicon tip, Mancevski says. He sees no reason researchers should not be able to make single-wall nanotubes, which would have a diameter of 1 nm.

Still Using Optics

Another group, at the National Institutes of Standards and Technology (NIST; Gaithersburg, MD), is working on extending optical microscopy down to the same levels. They use a combination of brightfield microscopy and scatterometry to measure features. Using low-numerical-aperture illumination from a 436-nm source, they produce a plane wave that hits the wafer and is scattered by the features. The intensities from various plane waves, which create patterns of constructive and destructive interference in the space above the wafer, give them data that adds up to an image.

Rick Silver, leader of NIST's scatterfield microscopy project, says the method has proved able to tell the difference between lines 38-, 39-, and 40-nm wide. Simulations show that lines 10- to 20-nm wide should not be a problem, either. Because the approach combines two methods used currently, it will be easier for semiconductor manufacturers to adopt and will probably enter wafer fabs in the next few years, Silver says.

Working with SEMATECH, NIST has also developed a set of standards to measure features down to 40 nm. The standards would be used to calibrate the tools used in metrology. "Integrated circuit features have shrunk so much over the last 20 to 30 years that we've got to the point that there are no standards available," says Michael Cresswell, a physicist in NIST's semiconductor electronics division.

To create their ruler, NIST scientists used a selective etch material that removes silicon in all but one crystal lattice orientation, producing lines that are almost atomically smooth. The spacing of silicon lattice planes is known, so it is just a question of illuminating the etched silicon with a high- energy beam of electrons and counting the planes to know how thick the materials are.

"They came out nice and straight and relatively smooth," Cresswell says.