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Micro/Nano Lithography

Removing the mask

Electron projection lithography uses an array-based direct-write approach to provide an economical maskless method for small-volume fabrication at the 65-nm node and below.

From oemagazine March 2002
28 March 2002, SPIE Newsroom. DOI: 10.1117/2.5200203.0006

For chipmakers and equipment vendors alike, the new International Technology Roadmap for Semiconductors (ITRS) reveals that keeping up with Moore's law will be an increasingly expensive proposition. It appears that the costs of not only tools but of photomasks (reticles) are poised to skyrocket. In fact, the extremely complex reticles that will be required to extend optical lithography below 100 nm will make the cost of ownership impractical for low-volume applications.

Until about 2007, the ITRS sees continued evolution of traditional optical lithography as the most likely lithography solution, in spite of growing costs. Because neither 157-nm nor extreme-ultraviolet (EUV) systems operating at 13.4 nm will be ready for volume production, critical layers down to the 65-nm node will have to be imaged with 193-nm argon fluoride (ArF) excimer laser scanners. Pushing ArF technology to the 65-nm node is certainly doable, but it will require extreme resolution enhancement technology (RET) to operate at very low k1 process factors. Extreme RET encompasses everything from complex optical proximity correction (OPC) and hard phase shift masks (PSM) to multiple exposures per process layer.

If 157-nm lithography is ready in time for insertion at the 65-nm node--that is, when lithography features are already less than half the wavelength--it will require extreme RET right from the start. EUV, with its very short wavelength, will allow more reasonable k1 factors, potentially avoiding the need for RET. Reticle blank defect density remains a critical issue for EUV, however, and could easily saddle users with the most expensive reticles of all. For these reasons, the cost of reticles for critical layers is expected to increase by as much as a factor of 10 over the next several years.

dropping the mask

How can companies producing application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) devices, with their typically small production runs, cope with these costs? One obvious solution is to eliminate the mask altogether. Maskless lithography poses many challenges of its own, however.

Direct-write lithography has been a topic of discussion for years, but the very small exposure field of a traditional e-beam tool offers such a low potential throughput that it has been dismissed in the past. More recently, electron projection lithography (EPL), which attempts to increase throughput by projecting an expanded e-beam spot through a stencil reticle, has gained prominence in the next-generation lithography arena. That approach still doesn't solve the basic problem: having a reticle in the first place.

Researchers in Canon's Nano-technology Center (Utsunomiya, Japan) have taken a different approach by developing a multicolumn, direct-write e-beam lithography method that not only eliminates the need for a reticle but enlarges the writing area to achieve throughput rates that are competitive with mask-based EPL methods.

Figure 1. The maskless lithography system uses an array of individually corrected beamlets to provide high-volume direct-write capability.

Instead of using reticles, this maskless lithography (ML2) technique effectively expands the coverage of a single electron beam by breaking it into a 64 x 64 array of micro e-beam columns that are controlled by CAD files (see figure). Electrostatic lenses provide a reduction factor of 50 through the e-beam column. Each beamlet is individually scanned over an area of 4 µm x 4 µm, which collectively forms a sub-field of 250 µm x 250 µm. Wafer stage scanning forms a main field of 0.25 mm x 3.5 mm. A continuous step, scan, and stitch sequence forms the desired exposure field at each shot.

Projection optics that allow an e-beam to be deflected far enough off axis to cover a 250-µm field would introduce significant curvature and distortion into the image field. To avoid these aberrations, Canon has developed a new correction lens array (CLA) that locally controls each of the 4096 beams, varying the correction as a function of distance from the original axis. The CLA consists of a two-dimensional aperture array, a two-dimensional deflector array, and a pair of two-dimensional electrostatic lens arrays, fabricated with a direct extension of present-day silicon and micro-electro-mechanical systems (MEMS) manufacturing technology. Placed between the collimator lens and the reduction optics in the e-beam column, the CLA generates a plurality of intermediate images of the electron source.

The deflectors and the lenses of the CLA can be electrically activated individually to control each micro beam. Adjustments to the focal length of each micro beam column control the position of the image along the z axis to compensate for field curvature in the reduction optics. The physical dimensions and spacing of the CLA electrodes are selected to compensate static distortion while the x and y deflectors electrically compensate dynamic distortion.

Electron beams from the CLA are incident on reduction optics through the blanking aperture array, which can individually control beam transmission electrically with a blanking aperture. The reduction optics are composed of two symmetric magnetic doublet lenses. These optics form a plurality of final images on the wafer as if the field curvature and the distortion of the reduction optics were eliminated. A deflector fitted on these optics simultaneously deflects the final images to scan the wafer. The CLA, in effect, creates an intermediate field curvature and distortion characteristic that exactly cancels the aberrations that normally occur in electrostatic reduction optics, producing a well-corrected image.

A high accelerating voltage allows the use of single layer resists, although this results in decreased resist sensitivity and wafer heating. In order to avoid these effects while maximizing the throughput of the CLA system, we selected an accelerating voltage of 50 kV, as it is the lowest voltage that allows high aspect ratio structures to be fabricated. Also, a high reduction ratio reduces the difficulty in fabricating the CLA and the instability of beam positions on a wafer due to thermal and electrical drift in the CLA, although increased demagnification increases column length. A reduction ratio of 50 was chosen to optimize the tradeoffs between fabrication, performance, and column length.

ML2 is not intended as a replacement for other optical or next-generation lithography techniques. Rather, the technology is targeted to critical layers in low-volume production and development applications. The relatively large depth of focus provided by e-beam lithography also makes it attractive for certain process layers such as dense, sub-100-nm contact holes, since there is little or no real estate available for assist features (OPC) or shifters on masks for these layers. oe

Phillip Ware

Phillip Ware is senior fellow, lithography strategy at Canon USA Inc., Irving, TX.