Researchers at Xerox Palo Alto Research Center (Palo Alto, CA) have developed a way to use micromechanical springs for chip-to-package interconnects. The new technology makes use of physical stresses created in the structure during deposition -- which would ordinarily be considered a disadvantage -- to create compliant fingers that can easily contact small bond pads.
So far, Xerox has successfully fabricated and tested microspring arrays with pitches as small as 6 µm, and researchers say it is possible to go smaller still. If the approach is successful and implemented soon, it could push this technology up to 10 years ahead of the Semiconductor Industry Association roadmap.
As lithographic feature sizes get smaller and packaged wafer sizes get bigger, there is an ever-increasing mismatch between processing power and interconnectivity. One reason for this is that in/out channels go through bonding pads at the chip edge. This means their number only grows as the linear dimensions of the chip grow. The number of components, on the other hand, grows with area.
Even if the size of the chip in/out was simply scaled to the lithographic feature size, this would present a major problem. But the situation is even worse: wire bonding and flip-chip soldering have reached a point where they are difficult to miniaturize further. The result has been an increasingly isolated processor. Though it can compute very quickly, it is becoming difficult to feed it with enough information to keep it busy (and get that data out again).
Figure 1. The MoCr finger springs up, thanks to stresses induced during fabrication. The remainder stays down because of the passivation layer, which selectively prevents releasing when the structure is dipped in HF.
The new Xerox technology improves the situation by increasing the number of interconnects that can run along a single edge by an order of magnitude, and maybe more. The basic idea is shown in Figure 1. First, a thin film of the alloy Mo0.8Cr0.2 is deposited onto a substrate that is precoated with a release layer of Si nitride. The stress in the 1-µm-thick film is deliberately manipulated during sputtering by gradually increasing the pressure. This results in more than 1 GigaPascal compressive stress at the bottom, shifting to over 1 GPa tensile at the top.
Figure 2a. Part of an array of 1000 microsprings formed by photolithography and thin film processing. These fingers have an 80-µm pitch and rise 60 µm from the substrate (within ±1 µm).
Figure 2b. Similar array, this time scaled down to a 6-µm pitch. The springs are 30-µm long, about 0.3-µm thick, and the top surface is coated with gold to increase conductivity.
The film is then lithographically patterned as long thin fingers and, by etching away the Si nitride, the ends are released. As the fingers are detached from the substrate, the stress is removed. Where there was compressive stress, the structure can now expand, and where it was tensile, the film can now contract. As a result, the finger curls to point upward (see figures 2a and 2b). The amount of curl, as determined by the stress gradient, is engineered so that the tips of the springs incline to no more than about 70 degrees. This causes them to roll out flat instead of bending over backwards during assembly.
Figure 3. One packaging possibility is to have the chip bonded to the microclaws and then covered with an "encapsulation can". The fins would allow heat sinking while the can itself would prevent contamination and minimize shocks to the springs.
These fingers can now be used to directly contact bond pads on a chip, which can be done in several different ways. In one experiment, the chip was simply pushed down onto the microclaws and held there using an overcovering and adhesive; the contacts were sustained solely by the force of the springs pushing against the bond pads. In another experiment, the bond pads were made of evaporated Indium and so the fingers were soldered in place after heating. Once the bonding was complete, the microsprings alone were enough to keep the chip in place (as well as electrically contacted). However, the package shown in Figure 3 is the most likely for practical use; not only does it protect the chip/package interface from contamination, but it also allows heat to be dissipated.
The 6-µm pitch microspring arrays, if put into production, could already allow more than 6500 chip-to-package in/outs on a chip of 1 cm2. The SIA roadmap, on the other hand, predicts just 4800 channels for a much larger chip by 2010. In addition, if it is ever needed, researchers should be able to scale the technology to even finer dimensions. Their feature sizes are currently limited by their lithography equipment, they say, not by anything more fundamental.
1. Donald L. Smith and Andrew S. Alimonda, A New Flip-Chip Technology for High-Density Packaging, Proc. 46th Electronic Components and Technology Conf. (IEEE: Orlando, Florida, May 1996), pp. 1069-1073.
2. Donald L. Smith, David K. Fork, Robert L. Thornton, Andrew S. Alimonda, Christopher L. Chua, Clarence Dunnrowicz, and Jackson Ho, Flip-Chip Bonding on 6-µm Pitch using Thin-Film Microspring Technology, Proc. 48th Electronic Components and Technology Conf. (IEEE: Seattle, Washington, May 1998).
Sunny Bains is a scientist and journalist.