ILLUSTRATION BY PETER BENNET
Lithography is used in the manufacture of integrated circuits (ICs) to transfer circuit patterns from a mask to the silicon surface. The smallest feature size a system can print is described by
Feature size = k1 λ/NA
where λ is the wavelength of the illumination, NA is the numerical aperture of the objective, and k1 is a proportionality constant that depends on the photoresist, specific system illumination characteristics, mask geometries, and manufacturing processes. For optical lithography, the characteristic wavelength has decreased from 365 nm to 248 nm to 193 nm and is currently migrating to 157 nm. Lithographic steppers operating at 157 nm are expected to print 100-nm features and perhaps 70-nm features using phase-shift masks and optical proximity correction (OPC).
Extreme ultraviolet lithography (EUVL) further extends optical lithography by using wavelengths in the range of 11 to 14 nm to shrink the size of features printed while maintaining k1 values at acceptable levels. An EUVL system currently under development by a European stepper manufacturer, for example, uses an EUV wavelength of 13.4 nm to theoretically print features much less than 30 nm using a 0.25 numerical aperture (NA) camera, without the use of OPC.
Although EUVL is similar to optical lithography, the reduced wavelength introduces several unique challenges. All materials are strongly absorbing at 13.4 nm; therefore, EUVL systems require vacuum operation. In addition, optics and photomasks must be reflective and coated with distributed quarter-wave Bragg reflectors.
Figure 1. Laser-generated plasma produces a 45 eV plasma that emits visible and EUV illumination.
For the EUVL system under development at the U.S. Department of Energy National Laboratories in Livermore, CA, a high-power neodymium-doped yttrium aluminum garnet (Nd:YAG) laser beam focused on a xenon gas, liquid, or solid target produces a 30 to 45 eV plasma that emits visible and EUV illumination (see figure 1). A condenser consisting of multilayer coated collector and grazing incidence mirrors collects and shapes the EUV beam into an arc field 6-mm wide by 104-mm long to illuminate the reflective mask or reticle. A low-expansion reflective reticle clamped to a scanning reticle stage moves the mask across the illumination beam, and a reflective optical system with aspheric components produces a 4X reduction of the mask image. The scanning wafer stage containing a semiconductor substrate coated with EUV-sensitive photoresist scans the wafer across the EUV beam in perfect synchronism and at one-fourth the speed of the scanning reticle stage.
To prevent the buildup of carbon on the reflective surfaces in the presence of EUV radiation, it is necessary to control the partial pressures of hydrocarbon-containing gases in the vacuum. Since the reflection of EUV from the reflective surfaces is less than 70%, the deposited EUV flux causes localized heating of the reticle and optical surfaces; this necessitates thermal management of critical surfaces. In addition, the velocity and position of the magnetically levitated stages must be controlled with nanometer precision.
The EUV LLC (a consortium of integrated-circuit companies consisting of AMD, IBM, Infineon, Intel, Micron, and Motorola) has built an Engineering Test Stand (ETS) at the DOE Virtual National Laboratory (consisting of Lawrence Berkeley, Lawrence Livermore, and Sandia National Laboratories; Livermore, CA). This system demonstrates all of the components and subsystems to enable EUVL in a full field scanning alpha tool (see table on page 24). The completed ETS consists of two major environmental enclosures, a source chamber or illuminator, and the main exposure chamber containing the reticle stage, wafer stage, and projection optics. The illuminator is isolated from the main chamber by a membrane-type spectral-purity filter that removes the out-of band radiation and provides an environmental barrier between the two systems.
The ETS contains approximately 100 sensors, including temperature, vibration, flux, and source-position sensors; a through-the-lens imager; an aperture viewing sensor; a reticle dose sensor array; a wafer dose sensor; and an aerial image monitor.
Although witness-plate data indicates that the ETS environment is benign in the absence of EUV radiation, short wavelength illumination in the presence of water vapor can trigger EUV-induced oxidation of the silicon-terminated molybdenum/silicon multilayers on the optics. The team has used gases such as ethanol to prevent oxidation and atomic oxygen or hydrogen to remove contamination and provide in-situ cleaning. Early ETS tests indicate that the partial pressure of gases with atomic masses greater than 44 is below 10-11 torr in the vacuum environment.
Figure 2. This image of a wafer patterned by ETS shows 100-nm features printed by step-and-scan. Since the image uses a dark field mask, small features, and large die size, only the largest surrounding clear field borders are visible in the wafer and full-field photograph. (LBNL)
The initial scanned 100-nm images were printed in a step-and-scan mode (see figure 2) using an extended deep UV experimental resist. Each full-field image covers a die site of 22-mm wide by 32.5 mm in the scan direction.
Currently, we are upgrading the ETS with an improved set of optics. The optics have been tested in a static microfield exposure station at the Advanced Light Source (Berkeley, CA). In this system, the scanning illumination system can be adjusted to tailor the partial coherence and pupil-fill illumination. challenges ahead
Although substantial technical progress has been made and essentially all aspects of the technology have been demonstrated, there are several remaining challenges that must be addressed to assure the successful development of production equipment to support 50-nm IC manufacturing. The challenges include providing incremental technology extensions to improve the production tool throughput and cost of ownership, accelerating fabrication of beta and production tools, and developing the commercial resist, mask, and metrology infrastructure.
The EUVL effort requires incremental technology extensions to improve mirror reflectivity and lifetime, system environmental control, source efficiency, power, lifetime, and spectral-purity filter efficiency. The target improvements include 70% reflectivity multilayer coatings with good thermal stability, environmental control to prevent carbon deposition and/or in situ cleaning methods to sustain five year mirror lifetimes, EUV source power to support a tool throughput of eighty (80) 300-nm wafers per hour, and filters to attenuate non-EUV wavelengths to provide spectrally pure EUV flux for reticle illumination. Volume optics fabrication and wafer and reticle stage accuracy also require evolutionary technology advances.
Major EUVL technology development began in 1997, with the goal of supporting the 100-nm process with beta tools by 2003 and production tools by 2005. Since then, the industry has extended 248-nm and 193-nm technologies to print smaller features while simultaneously developing 157-nm technology. These efforts have shifted the targeted process introduction for EUVL to the 50-nm node.
In addition, the production of beta EUVL tools has been delayed for a number of reasons. The technology is not a simple extension of optical lithographyadditional resources are required, and the development of 157-nm lithography at the same time as EUVL dilutes and competes for the available resources. Materials issues at 157 nm and its possible extension to smaller feature sizes introduce timing uncertainty. The downturn in the world economy has reduced R&D investments, and the lack of competition in developing the first EUVL tools has reduced the competitive pressure. The readiness of the infrastructure to support the beta and production lithography tools is also uncertain. In addition, infrastructure suppliers have delayed their investments because of the uncertainty in beta and production-tool availability, as well as related market timing and required production ramps. Most infrastructure supplier companies are relatively small and cannot afford to develop tools far in advance of the required volume use. The interrelation between lithography-tool and infrastructure-supplier decisions causes a cyclical decision process and additional delay.
It is not enough to have a stepper. It is necessary to establish the resist and mask infrastructure to support EUVL in production. Imaging experiments using the ETS and 10X microsteppers have demonstrated the extendibility of modified deep UV (DUV) resists. Although some photoresist optimization will be required to reduce line edge roughness, photoresists for EUVL are not considered to be a problem. However, considerable development is still required to provide low-defect commercial masks.
The reflective EUVL mask requires a number of additional manufacturing steps over conventional binary masks and, hence, faces commercialization challenges. The masks begin with a low thermal expansion substrate material similar to ULE or Zerodur. Shaping, polishing, and application of multilayer and absorber coatings produce ready-to-write blanks. The mask patterning, inspection, and repair processes use extensions of conventional mask patterning equipment. The small feature sizes necessitate extra care for the handling, inspection, cleaning, and repair steps. In addition, conventional optical pellicles used to protect the photomasks and the image plane will not work for EUV masks. Alternatives under consideration include thermophoretic protection for the mask inside the tool and use of a removable cover for storage and transportation.
We expect the mask blanks will be provided in a ready-to-write multilayer stack consisting of a resist-coated absorber, a protective buffer layer, an oxidation-resistant capping layer, and low-defect multilayers. Mask blanks will be patterned using conventional e-beam mask writers, inspection will use reflective DUV inspection tools, and mask repair will use focused-ion-beam methods. Although all areas require additional development, the present rate of defect reduction and progress in developing new inspection tools should support production of low-defect masks for early EUVL process development using beta tools by 2005. EUVL advantages
EUV lithography has many advantages over other optical lithographies proposed for printing sub-70-nm features. For example, EUVL leverages much of the learning and supplier infrastructure established for conventional lithography. The technology achieves good depth of focus and linearity for both dense and isolated lines with low-NA systems without OPC. The robust 4X masks are patterned using standard mask writing and repair tools, and similar inspection methods can be used as for conventional optical masks. The low thermal expansion substrates provide good critical dimension control and image placement. Experiments have shown that existing DUV resists can be extended for use with EUV.
All elements of EUVL technology have been successfully demonstrated in a full-field "proof of concept" lithography tool. This demonstration dramatically reduces the technology and implementation risks associated with the development of commercial tools. Even though continued technology development and improvement will be required as the technology moves from the demonstration phase to production, there are no known showstoppers that will prevent EUVL from becoming a manufacturing reality. oe
The work was performed by the University of California-Berkeley, Lawrence Livermore National Laboratory, and Sandia National Laboratories under the U.S. Department of Energy Contract Nos. W-7405-ENG-48 and DE-AC04-94AL85000, and Lawrence Berkeley National Laboratory under the auspices of the U.S. Department of Energy Office of Basic Energy Sciences. Funding was provided by the Extreme Ultraviolet Limited Liability Company under a Cooperative Research and Development Agreement.
Charles Gwyn is program director for the EUV LLC in Livermore, CA.