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Micro/Nano Lithography

Eric Beyne: Advanced packaging and 3D integration for chip design

The rapid development of 3D chips presents new challenges still to be overcome in stacking, scaling, and performance.

24 April 2013, SPIE Newsroom. DOI: 10.1117/2.3201304.05

Eric Beyne received a degree in electrical engineering in 1983 and the PhD in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986 he has been with IMEC in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies.

Currently, he is program director of IMEC's 3D System Integration affiliation program. The team performs R&D in high-density interconnection and packaging techniques focused on "system-in-a-package" integration, 3D interconnections, wafer-level packaging, RF front-end design and technology using integrated passives and RF-MEMS as well as research on packaging reliability including thermal and thermo-mechanical characterization.

He is an active member of the IEEE-CPMT society, president of the IMAPS-Benelux committee and member of the IMAPS-Europe Liaison committee. He served as general chair of the IEEE-CPMT European System Technology Conference, ESTC2012 in Amsterdam.