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Micro/Nano Lithography

Yan Borodovsky: Moore's Law At and Beyond 5nm

A plenary talk from SPIE Advanced Lithography 2018.

8 March 2018, SPIE Newsroom. DOI: 10.1117/2.3201803.02

Yan Borodovsky, SPIE Fellow, Intel Senior Fellow (Retired) (USA)

In this plenary session, Yan Borodovsky (Intel, ret.) begins by pointing out that for more than 50 years, the semiconductor industry ecosystem has supported high-volume manufacturing of ICs that followed the famous Gordon Moore's exponential transistors density and cost rate of change prediction. Yet, resolution and "raw" EPE control of lithography exposure tools used in high volume manufacturing were, and still are, lagging IC patterning needs as demanded by the economy of Moore's Law for last 20+ years.

As a result, the ever more complex patterning techniques that result in additional wafer cost were introduced at every node driving intra-node wafer cost growth from a traditional 10% to 30% or more. This in turn resulted in the need for significant change in the approach to IC design layout rules definitions, higher capital equipment reuse rates, significant change in CAD and mask making equipment, and other important changes to wafer and mask making infrastructure.

Due to the complex relations between patterning costs, device design rules, device architecture, various and different sets of imaging, the etching, thin films and CAD tools and materials needed to support various existing and expected to materialize routes of wafers processing IC manufacturers face difficult choices. This is true in regards to managing the R&D resource allocation capable to identify optimal strategy for 5nm node and beyond that will continue the historical trend of IC inter-node rate of area density growth and cost per transistor reduction. All of this while keeping inter-node cadence within historical 2-3 year time frame.

NF phase shifts illumination angle dependence

With the advent of new for-HVM patterning approaches such as EUV, DSA, and selective deposition, the level and impact of stochastically introduced defects on process yields, if not contained, may rise dramatically with detrimental impact to future nodes development cycles and wafer costs.

Correspondingly, the resurrection of old design methods (redundancy), expansion of existing ones (built-in-self-test) as well as development and introduction of new methods and tools, specifically targeting understanding and mitigation of such defects during development as well as HVM, needs to be deployed starting now and be employed in the not so distant future.

Introduction of such new-to-HVM patterning techniques and maturation of processes build on its basis during the next technology nodes starting with 5nm will see progressively larger portions of computing content on the chip moving from von-Neumann architecture to different ones such as neural nets and neuromorphic computing that might or will exhibit significantly different yield sensitivities from von-Neumann portion of the chip.

new-to-HVM patterning techniques

Understanding such differentiated sensitivities to stochastically introduced defects in advance needs to be developed in order to properly design process development test chip and defects testing methodology as well as corresponding HVM wafers disposition approach.

Before retiring in 2015, Yan Borodovsky was an Intel Senior Fellow and Director of Advanced Lithography in Intel's Technology and Manufacturing Group, responsible for directing Intel's multi-generational advanced lithography definition and progress.

He received his master's degree in Solid State Devices and Physics from Politechnical Institute in Tula, Russia, in 1971. He then joined the Nuclear Research Institute of the Ukrainian Academy of Science, Kiev, as an engineer involved in the research and development of solid state spectrometers of nuclear radiation. He left the former Soviet Union in 1979 to work at Syncal Corp. developing high-temperature semiconductor materials for deep space thermoelectric conversion devices.

In 1982, Borodovsky joined Advanced Micro Devices as a lithography staff engineer. In 1985, he moved to Oregon to join ATEQ Corporation, where he designed and developed optical systems and optical testing equipment for the original CORE 2000 Laser Writer.

He is a Fellow of SPIE and has authored numerous papers in SPIE Proceedings since 1995.

In 2016, Borodovsky received the Frits Zernike Award for Microlithography for his work in advancing multigenerational lithography process solutions and his key contributions to patterning approaches and layout design rules.

Related SPIE content:

Yan Borodovsky: The various paths to next-generation lithography
The march to the next node will depend on overcoming barriers and exploiting multiple solutions before "next generation" becomes "this generation," says Intel's lithography director.